ZEN 5 has a 3D V-Cache Secret

In-depth silicon analysis of AMD's Zen 5 Ryzen 9000 CPUs based on ultra high-res die shots from @FritzchensFritz.

0:00 Intro
0:59 Zen 5 Chiplet layout
2:42 IO-die - Overview
3:21 IO-die - Silicon analysis
6:05 CCD - Overview
9:42 TSVs & TSMC SoIC
10:34 Zen 5 X3D / 3D V-Cache
16:04 Zen 5 CPU Cores
18:28 Final thoughts

[Violet-ui]

The resolution of those die shots is actually insane

[Steamrick]

It's a pity that this kind of deep-dive content has such a niche audience. Your channel deserves to be far bigger than it is.

[derauer]

Such a nice channel! Wish I knew it earlier :D Great video!

[ckmishn]

Apparently the puzzle has been solved. The reason there's so few TSVs is because the V-Cache is underneath the CCD, so the CCD doesn't need power TSVs, just data.

[Poctyk]

Double stacked 3D cache?
Welcome back, consumer HBM

[aapje]

Having 2-layer 3D-cache makes sense given the rumors that the new X3D-CPU's can boost higher. More compact 3D-cache that is further away from the compute cores would be less sensitive to heat coming from the compute cores.

[NootNoot.]

The 35% reduction in L3$ is quite an amazing feat. Also, with the TSVs, this is another "generational" change, and I'm impressed with how far R&D goes to improve it unlike the IOD.

[jtd]

OK, you have managed to engage my interest for Zen 5. This is the kind of analysis I have been missing since Jim from @AdoredTV stopped making tech content. That and his "Awright, guys, how's it goin'?".

[blazer]

AMD kept saying it was a redesign. Your video highlights this. It seems like most people can't see past minimal IPC uplift and the introduction of full avx512. Excited to see what 3Dvcache brings for this gen.

[JMurph]

Gosh those super tight-in shots near the TSVs just blew my mind. Reminds me of just how exquisitely complex modern processors are, and of course it's a tour de force in macro photography.

[dareliv_nlove]

Came back here immediately after hearing from GamerNexus that Zen 5 X3D might be flipping the cache & ccd. Potential great explanation for the differences you've discovered: If the cache is no longer on top, less circuitry needs to go through the silicon itself! 😊

[DanKaschel]

"I've inserted chapters so you can go straight to the sections that interest you." Never subbed so fast.

And watched the whole thing anyways 😂

[vardhansuroshi]

It took me a whole undergrad just to understand some terminologies present in video. "Just Understand". Semiconductor is quite interesting. Stuff like these make me realize there is so much more to explore. I hope more people find such stuff interesting.

Hey YouTube algorithm push this video. I hope "this" helps.

[SarahGoogleandYouTube]

You are probably the most interesting tech researcher I have come across on the internet. I love how you take complex topics and break them down for people like me. It's truly valuable.

[SarahGoogleandYouTube]

BTW, your presentation is now top-notch and professional. You have grown tremendously.

[NootNoot.]

@HighYield and @FritzchensFritz the impeccable duo!

[davidGA殿]

Bro, the images are bonkers. They look so good, even after zooming in that much.
Thanks for the explanation of the chips, it makes the images even more amazing.

[humbleeagle]

AMD like had extra SI vias for the previous generations to increase yields. Now that the process has matured, they don’t need them. The extra vias could have caused the power problems of the previous gens that restricted over clocking.

[AOTanoos]

Great Video, Thank you ! Side note, at 7:19 you wrote Core 4 twice on the right, instead of Core 5 :)

[GreyDeathVaccine]

+1 for stats
Thx for your work. I love topics about internals 🙂