AMDs NEW CORE strategy: Efficiency cor...*backspaces*… CHIPLETS?

THIS ISN'T CONFIRMED!!! Just a prediction by the Wizard Computer Janitor Wizard Wendell.

With the launch of Bergamo with the new 3d V-cache, how far could AMD progress the innovation of desktop CPUs? How screwed is Intel? Tune in and find out!

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Intro and Outro Music: "Lively" by Zeeky Beats

Edited by Autumn

[spidersj]

If AMD can implement 24 full fat cores at a 35W power envelope with decent clock speeds, the laptop space will belong to AMD as well as desktops.

[jp-nypd]

You've essentially got a fully customizable CPU platform that can be completely transparent to the underlying OS. Just pick the CCD that first your needs (2/4/8/12 chiplets), add one CPU chiplet (which now has basic video built in with zen4), and whatever other AMD chiplets you like. Want 10 AI chiplets and 2 CPU chiplets? Sure, just order 5000 of them.

[danknemez]

Regarding the IOD - difference between GMI "logical" and "physical" layers. You can funnel the data of multiple CCXs through the same physical IFOP link, that is what Bergamo does.
Afaik the reason why we "only" got 8 CCDs is that there are only enough CCMs (cache coherent master) blocks on the IOD to service 16 CCXs, not 24.

[SAFFY]

The CPU space is very exciting indeed. It will be interesting to see what route the 2 companies will take.

[alexmannen]

intel heres our 400w cpu amd heres our 65w being twice as fast

[xXiamsniperXx]

Imagine an AM5 "7955x3D" an 8 cores zen4 3D V-cache and a 16 zen4c cores the ultimate gaming/workstation chip

[RinoaL]

Wendell, you are really at your best ever with presenting a video. I've been watching you for years, and your methods of presenting and such are very refined now. You look great on video too. Just thought I'd let ya know.

[SeventhCircle]

Wouldn’t mind seeing a 3D cache ccd at 8 cores and a 16 core zen4c ccd on one chip.

[rem]

I remember Tom from “Moores law is dead” mentioned how AMD will do a hybrid design for their laptops and APUs but there are no plans for the desktop as there isn’t much of the same efficiency demand for desktop but it could be for after Zen 6. He might have mentioned it to you when you were on the podcast Broken Silicon with him last time

[solidreactor]

Performance CCD + Efficiency CCD + HBM-D (HBM die) would be interesting!

I wonder if each CCD could have 2 different CCX design in it, one CCXp and one CCXe (performance / efficiency CCX).

[joshxwho]

Okay, from now on I'm calling bergamo "burger mo" or "mo burgers".

[Packetlust]

It would be cool to see what 16 Zen4c cores paired with on package HBM2 (or newer) could do

[macbeardie]

Awesome, I hope this is AMD's plan.

Although an AMD system with mixed cores as you describe would have no problems with booting or software compatibility, it would still need an updated process scheduler to take full advantage of the architecture. So not QUITE plug and play, but a lot closer than designing a completely new core.

[snap_oversteer]

I really hope AMD will actually contribute to coreboot as they have promised multiple times as I'd much rather run current gen AMD CPU rather than Alder Lake, but last AMD CPUs that can run coreboot are some ancient Opterons...

[Lionheart]

Pretty amazing, but not only that, I wonder what future AMD APU's there will be. AMD"s original marketing slogan with ATI was "The Future Is Fusion" Took em a while but they finally got there.

[Fenrasulfr]

This sounds like a dream scenario where we get ultra efficient gaming cpu's.

[DanKotowski]

Can you add WHr/kernel to your benchmarks? As a recent transplant from US to EU, my homelab priority is no longer “time to build” but “lowest monthly power bill”. The idea of picojoules/bit is cool for the academics but the rest of us have bills to pay

[giorx]

Indeed AMD have a plethora of choice for future products using the c cores and the 3d cache. My thought is that, for consumer products the Zen4c will be used for mega Apus on laptops.

[doublecinco]

There's been a rumor about a Strix Point Zen 5 APU that has normal 5 and 5c cores on one chip. I had thought it was mainly for maximizing multi-threaded perf per die area while keeping high single threaded performance, but it looks like it should be awesome for overall efficiency as well.