PD Lec 53 CTS Constraints | Spec File | Clock Tree Synthesis | VLSI | Physical Design

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This is a 53rd video of physical design series and mainly related to clock tree synthesis. In this video, we discuss about constraints of cts and spec file and constraints in cts.
Please ask your doubts in comments.

Placement in Physical Design [Interview Quiz]:

PD Lecture series playlist:

Here's a link for Full STA series [till advanced level]:
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Thank you for your efforts this video is most help full for me

bmallu
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with recent interview process we can emphasise on different types of clock tree (mesh, mscts, pie etc.) and differentiate on basis of usage, ease, power etc

rashipandey
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How we can decide the target skew and target latency .. How to set those numbers.

JyothiPrasadsLifestylevlogs
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I have a few questions,
1. On what basis do we decide the skew/latency values?
2. If talk about NDR, suppose we use 2w2s for cts, it means not 2 clock nets will have 1w1s, but when we go to route, The space (2s) is used by signal nets or not?

CTS will be like this:-
----clock net----


----clock net---

Are we expecting a fully routed design like the below one?
OR
----clock net----


----clock net---

Thanks

japeshsingla
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Sir, how we know the target skew and target insertion delay? I think top level people will give these targets... Am I right or not...
How should I give answer if this question will ask by an interviewer to me...
Please, give reply...

praveengupta
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Good day sir, may we have a video which talk about buffer vs inverter?

alanlim
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How do you guys learn, is there any efficient way? I watched the video and tried to do the interview and found that I made a lot of mistakes/

PEACEGGXD