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PD Lec 67 - Global and Detail Routing | VLSI | Physical Design
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This is a 67th video of physical design series on Physical Design. In this video, we discuss about routing stages and global and detail routing. Please ask your doubts in comments.
Placement in Physical Design [Interview Quiz]:
PD Lecture series playlist:
Here's a link for Full STA series [till advanced level]:
This is a 67th video of physical design series on Physical Design. In this video, we discuss about routing stages and global and detail routing. Please ask your doubts in comments.
Placement in Physical Design [Interview Quiz]:
PD Lecture series playlist:
Here's a link for Full STA series [till advanced level]:
0:10:48
PD Lec 67 - Global and Detail Routing | VLSI | Physical Design
0:05:42
PD Lec 38 - Global Route Congestion | VLSI | Physical Design
0:08:20
PD Lec 66 - Routing Concepts | VLSI | Physical Design
0:06:48
PD Lec 65 - Introduction to Routing | VLSI | Physical Design
0:08:51
PD Lec 64 - Skew Groups | CTS | VLSI | Physical Design
0:08:55
PD Lec 51 How to balance skew and latency? | CTS | Clock Tree Synthesis | VLSI | Physical Design
0:07:16
PD Lec 36 - Cell Density of std cells | VLSI | Physical Design
0:07:49
PD Lec 27 - Sanity Checks -2 | Floor-planning | VLSI | Physical Design
0:06:21
PD Lec 57 Clock Gate Enable Checks | CGC Paths | CTS | VLSI | Physical Design
0:10:57
PD Lec 56 Clock Gating Checks | CGC Paths | CTS | VLSI | Physical Design
0:11:15
PD Lec 44 - Timing Fixes in placement | Part-2 | VLSI | Physical Design
0:14:31
PD Lec 17- Floorplanning & IO Placement [part-3] | VLSI | Physical Design
0:09:19
PD Lec 53 CTS Constraints | Spec File | Clock Tree Synthesis | VLSI | Physical Design
0:08:44
PD Lec 29 - Cell Orientation and Flipping | Placement | VLSI | Physical Design
0:05:54
PD Lec 45 - Spare Cells | Physical Only Cells | VLSI | Physical Design
0:10:48
PD Lec 59 - Master, Generated and Virtual Clocks | Type of clocks | VLSI | Physical Design
0:05:17
PD Lec 62 - CTS Analysis | VLSI | Physical Design
0:05:40
PD Lec 28 - Sanity Checks -3 | Floor-planning | VLSI | Physical Design
0:09:24
PD Lec 25 - Physical Only Cells | Floor-planning | VLSI | Physical Design
0:06:17
PD Lec 7 - Physical Design Inputs Overview | Tutorial | VLSI | Physical Design
0:05:46
PD Lec 58 Integrated Clock Gates | ICG | CTS | VLSI | Physical Design
0:06:06
PD Lec 61 - Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design
0:01:09
PD Lec 48-Interview Questions | placement | VLSI | Physical Design
0:04:04
PD Lec 55 Power Dissipation in clock tree | Clock gating | CTS | VLSI | Physical Design
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