PD Lec 32 - Placement of std cells | VLSI | Physical Design

preview_player
Показать описание
#vlsi #academy #physical #design #VLSI #semiconductor #vlsidesign #vlsijobs #semiconductorjobs #electronics #BITS #qualcomm #netlist #lef #lib #floorplan #icc2 #synopsys
This is a 32nd video on Placement in Design in VLSI spectrum.
Please ask your doubts in comments.
PD Lecture series playlist:

Here's a link for Full STA series [till advanced level]:
Рекомендации по теме
Комментарии
Автор

In congestion driven placement, cells are spread away in order to reduce the congestion. Means it will require more area than normal(without congestion driven) placement. Then how it is prefered when area is less? Where am I wrong?

pratikpawar
Автор

How do we know whether design is time driven or congestion driven?

rnareendra
Автор

Good explanation sir👏👏.
sir Are you having any standard cell library with you which includes AOI and OAI gates. Can you please send me sir.. Please.

-ds-nagamanicholleti
Автор

All your videos are very use full and well explained. Thanks for the effort sir

pvignesh