PD Lec 47 - concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design

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This is a 47th video on physical design series and mainly related to placement of std cells. In this video, we discuss the technique of useful skew [concurrent clock and data optimization] related to timing fixes in placement stage.
Please ask your doubts in comments.

PD Lecture series playlist:

Here's a link for Full STA series [till advanced level]:

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sir, i feel the ccd topic was not sufficiently discussed. can you please elaborate further

vikineo

Can you please cover below topics :: clock domain crossing, synchronizers, RTF's & lock up latches ?

neerajmishra-dozq

Hi, Your videos are very helpful. Can you please post videos on Antenna Effect, Electromigration, Cross talk, IR drop etc., Thanks in advance.

compat

if FF2 is adding 50ps, is it adding through adding some buffer? Or How is the delay modelled?

montyi

Basically, Useful skew and CCD are kind of same. right.?

japeshsingla

At the end of the lecture, why AT becomes 940 and RT is 950? Why not AT=890 and RT=900, so as Slack=10ps?

SL-lqyh

Sir then what is mean by timing borrow concept

prakashbadhavath

Hello sir can you post videos on CTS. It will be very helpful. Thank you.

srinivasrahul

Can u pls tell me sir How does the CCD affect the area in placement?

sanjusingertelugu

What happens if i disable ccd in above scenario?

soorajjp

What is the difference between CCD and CTS than?

shubhangisingh

PD Lec 47 - concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design

PD Lec 47 - concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design

PD Lec 64 - Skew Groups | CTS | VLSI | Physical Design

PD Lec 62 - CTS Analysis | VLSI | Physical Design

PD Lec 55 Power Dissipation in clock tree | Clock gating | CTS | VLSI | Physical Design

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PD Lec 51 How to balance skew and latency? | CTS | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 54 CTS Exceptions | Float pin | Stop Pin | Exclude Pin | VLSI | Physical Design

PD Lec 46 - Useful Skew | Timing Fixes in placement | VLSI | Physical Design

PD Lec 24 - Power planning and power mesh creation| Floor-planning | VLSI | Physical Design

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PD Lec 45 - Spare Cells | Physical Only Cells | VLSI | Physical Design

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PD Lec 35 - Scan Chain Optimization | VLSI | Physical Design

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PD Lec 34 - place-opt understanding | VLSI | Physical Design

PD Lec 63 - Post CTS Optimization | VLSI | Physical Design

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PD Lec 61 - Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design