PD Lec 62 - CTS Analysis | VLSI | Physical Design

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This is a 62nd video of physical design series on CTS Analysis. In this video, we discuss about what we need to analyze in CTS, with some commands. Please ask your doubts in comments.

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Only thing never can be stolen is knowledge!! U feeding the pd hungers... Don't know what makes you motivated.. but u did such a wonderful job. Watched all the series. Do more and expecting the flow in tool point of view also. ❤️🎉👏👏

pamidipatisrikanth

Before CTS clock is ideal means all filpflops get clock at the same time there is no actual clock delay to reach flipflops i.e... simple skew is zero. But after CTS, clock can be propagated so reaching clock from clock port to clk pin of flipflops is different means skew will come into picture. So we have to fix hold violation after CTS only. Fix hold before CTS means watering to the plants in the rain (no use).
Please correct me if I'm wrong. And tell me perfect answer...

praveengupta

In the placement setup violation check only because the setup depends on the data path only . Hold depends clock path before CTS clock path is ideal so we calculate or check setup violation only .

chandiniranikuna

Thanks for clear explanation. I am thinking this whole day in my mind today.... Now I understand😉

tamilselvanselvaraj

Setup is dependent on clock period, so during placement stage ideal clock is assumed which has a clock period, hence setup is checked at placement stage.
Hold is dependent on clock itself i.e. it is only dependent on uncertainity(Skew+Jitter). Since Real clocks are not built during placement stage, Hold is not checked.

nishanthdoddamane

Why no hold check at placement stage - Because at placement stage skew is zero (ideal clock) . Looking at hold timing equation : Tclk-q + Tcombo > T-hold . This equation stands true at placement stage beacuse T-hold is always less than data path delay i.e sum of delay in flip-flop and combo delay. Only after we have skew ( +ve skew), chances of hold violations arise. Because at that time hold timing eqn would be Tclk-q + Tcombo > T-hold + skew .

zunaid

In placement stage also we can fix the hold but for fixing hold in place stage you need to add buffers to meet hold...
And after CTS stage the real skew comes into picture and hold will violates if skew is negative then again you need to fix hold in CTS stage by adding buffers..
The area of the core will be used more for fixing hold because you added in place, CTS stage the utilization will increase and the design cannot route...
And more cells will be added in cts_opt stage...

jettyharish

Sir in the placement stage clock is idols so we are not checking the hold.. After CTS clock is propagate so we have the practical clock.. This is why we do hold after CTS..

tamilselvanselvaraj

We have to check hold after CTS because here all clock nets are fixed and we have to fix the hold violations after final detailed routing because trial route netlength may change after detailed routing due to this some paths may fix.

lekha

At place stage negative skew will help hold

hillsandexploringscenery

ur explanaton is too good, ,sir i have a one question why we do cts before routing ?1)1st we do top metal layer for power routing, and we do middle metal layer for clock routing, and we do lower metal layer for sighnal routing like wise we do orderwise and also clock sighnal have recquired more width once we do cts means congeston occurs, flop goes to metastable state is it correct sir ?

if wrong or correction means pls give corect answer sir

NatrayanChinnalu

can I insertion delay is less then skew.?

patakha

PD Lec 62 - CTS Analysis | VLSI | Physical Design

PD Lec 62 - CTS Analysis | VLSI | Physical Design

PD Lec 63 - Post CTS Optimization | VLSI | Physical Design

PD Lec 49 - Introduction to CTS | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 54 CTS Exceptions | Float pin | Stop Pin | Exclude Pin | VLSI | Physical Design

PD Lec 51 How to balance skew and latency? | CTS | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 64 - Skew Groups | CTS | VLSI | Physical Design

PD Lec 52 CTS Algorithms | CTS | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 55 Power Dissipation in clock tree | Clock gating | CTS | VLSI | Physical Design

PD Lec 60 - What is crosstalk ? | CTS | VLSI | Physical Design

PD Lec 50 Clock Tree Synthesis | CTS | VLSI | Physical Design

PD Lec 61 - Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design

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PD Lec 30 - Interview Questions | VLSI | Physical Design