Analog Chip Design is an Art. Can AI Help?

Notes:
I say that digital design is roughly the same size. Sometimes they have to be different sizes for the purpose of optimizing of delay/speed - usually by a factor of 3 or 4. That has some interesting consequences in FinFET design but we can talk about that someday later.

Links:

[berniethompsonus]

This episode oozes all the things that makes Asianometry great. Expert, deep, quirky, silly, and interconnected.Thank you for what you do!

[Gameboygenius]

Ok, let's try to identify some of these images for fun.
0:06 A DC/DC converter module of some kind. Transformer and optocoupler in the middle of the board to isolate the primary (right) form the secondary (left). Could be for use in telco for converting 48 V to a local voltage like 5 V or 3.3 V for example.
0:13 Some analog chip produced by PMI (Precision Monolithics). Could for example be an opamp.
0:31 The title "analog delay" combined with delay stages taking opposite clock signals φ_1 and φ_2 points toward a BBD (bucket-brigade delay). This is an analog device delaying an analog signal by feeding it through a series of capacitors which each holds a sample temporarily before passing it on. I don't recognize the circuit. I would've loved for this to be either Serge's Wilson Analog Delay or Buchla's model 277 (modular synth devices) but it doesn't look like it.
2:09 As the title suggests, an analog multiplier circuit. What's neat about this circuit is that it's actually a logarithmic converters followed by a summer followed by an exponential converter. In other words, it turns a multiplication into an addition according to the laws of logarithms and exponentials: a*b=e^(log(a)+log(b))
2:51 Looks like the same analog delay circuit as in the title card. Through the magic of reverse image search, this turns out to be an early 1976 guitar pedal prototype circuit which inspired MXR delay pedals.
3:05 The title cards for two previous videos. To the left, the board for a HackRF One, a SDR (software defined radio) which can be used to receive various radio signals. To the right, something that looks very much like a computer motherboard, with PCI or RAM slots.
4:27 Looks like a RF demodulator going into an AGC (automatic gain control) then into an amplifier feeding a builtin speaker. Ie a radio receiver. The negative voltage supply (positive ground) combined with liberal use of transformers, suggests a vintage circuit.
5:00 LM317 internal diagram. LM317 is a classic adjustable, linear voltage regulator. The schematic of the internal diagram is drawn in the datasheet.
7:18 Looks like a circuit for exercising your understanding of Kirchhoff's Law in school. Fun stuff.
10:52 A delicious cake, which I'm informed may be a lie.
12:30 Looks like a sawtooth wave generator. The second opamp is setup as a comparator, which will trigger the MOSFET and reset the phase when the voltage goes above 2.5 V, plus a little bit of positive feedback to encourage the opamp a bit to work as a comparator, which it's otherwise reluctant to do. Also, screenshots are hard.
12:44 Not a schematic, but just a note that it's difficult for AI to generate grids apparently. The lines are wobbly and the lines never seem to line up on both sides when they're obscured by some object.
15:18 Interesting. I wonder what this is. Two CPU/FPGA/whatever devices hooked up to memory, by the looks of it. And then IDC headers. This is probably some industrial or test equipment, like the digital portion of an oscilloscope.

[jonpattison]

In the mid 80's I worked at a silicon design firm. Mostly 3 micron gate arrays. My boss and a really sharp engineer from the client company designed a modem chip. Their first silicon worked fine which elevated them past hero status to God of silicon design status. Mixed signal chip design is something like witchcraft.

Thanks for another great video!

[jaykita]

The complicity of analog design is worse when you include temperature sensitivities in the transistor and material performance. My old company (name withheld) included a Power On Rest circuit that gated power to internal logic so that it always started up in a known state. The circuit was updated in a routine design revision that passed all qualification tests across temperature and worked great in industrial grade applications, but came to a screaching halt when it was sold as an automotive product. Process variation of some lots allowed the temperature response of the POR to shift, locking the chip up when you turned it on in a narrow temperature window, A minor issue for a cell phone, but pretty painful if you are trying to unload VW's from a ship in the winter (the ECU wouldn't function). As you noted, analog design is an art, one where you have to know how all the paints mix and interact. Nice job on the presentation, I hope your father was able to retire happily.

[bradsalz]

As an analog/RF IC designer I can relate. About a dozen years ago when I was working at AMD our CAD group made an attempt to automate analog design to redesign chips shrinking to a smaller process node. It did this by interpolating the I-V curves to resize transistors. The results were laughably amusing and none of my IC design peers ever lost sleep worrying about design automation. Layout for analog circuits might be an even tougher nut to crack because an alogrithm would have to iterate on extracted simulation, layout, LVS/DRC checks, re-extraction, and back to simulation. Given the size of extracted netlists, I would expected the required hardware compute resources to require a supercomputer. LOL. But all of that was before AI. Fortunately, I'm close to retirement now so I expect to skate by just as your father did. Not so sure about the next generation of circuit designers, however ....

[jaqueitch]

The honor you show your parents is so wonderful

[kipmachale]

My perspective of 50 years of working in electronic industry is digital is a very narrow subset of analog. Resistance, and/or, impedance plus capacitance, and the one thing you left out in your talk is inductance. But you are correct and that it takes a few people with the artistry to do a good job in design.

[alex_hiller]

As an early career analog designer, I have to say that you generally got the design flow right, except that nowadays almost no one is using a paper and pencil to do anything significant. Usually things will be sized and played with in a simulator, experienced designers "have a feeling" about what sizing is going to work, and are usually right. The complexities of BSIM-BULK models (formerly BSIM6) means that doing anything on paper is fruitless, though there is some nice guiding principles in the EKV model. Reductions in supply rail headroom have also meant we have to do most things in weak inversion now, and that changes your current characteristic from quadratic to exponential, another weirdness that is different from what is taught in university.

AI training really seems hard to achieve, though probably not impossible considering what LLMs are doing these days. But one of the key problems is that there are many criterion for "good" and so in order for a computer to optimise, this optimisation has to be set up in the outset. This means that two different analog designers might have very different goals with an assistant AI, one might care more about their area specification, another might be more focused on how they are going to achieve their dynamic range spec with the power consumption spec. As you said, it's a very high-dimensional space, I'm not sure how one AI tool can really guide you through all of that. That's to say nothing on how you are attaining this dataset to train on, where's that coming from? Also, who is qualified to do the annotation of data for a dataset? Lots of hard problems to solve in this domain.

[giovanniguaitini]

I used to be an analog and mixed mode ic designer. I had LOTS of fun. I especially enjoyed the challenges of simulating the circuits properly. And what a feeling when the first silicon arrived on the bench and it worked exactly like in the simulator! Of course sometimes certain behaviors of the actual chip remained a mistery...

[AlexSchendel]

13:02 AlphaGo was not actually trained on huge datasets. The reason it is capable of beating the world's best players with *novel* techniques is because it was not trained by watching humans play. Instead, it played against itself and gradually learned over millions (or more?) iterations while grading its performance.

[Stuartrusty]

As an electronics repair tech for a large US manufacturer in the UK, I work on and use precision analogue electrical measuring instruments every day. I almost never gave any thought to the complex analogue designs inside the many many ICs used in this equipment. Being a designer of the circuitry in this high accuracy analogue equipment is a huge challenge in itself. The design engineers job is having to take into account parasitic capacitances, inductances and resistances. Having made a few analogue designs from discrete and IC components, I know how challenging some of these can be. I sometimes think it is all magic, and I have been in the industry since I left college in 1984.

I take my hat off to those who design analogue circuitry on a microscopic level, and am glad to see you honour your father in this piece.

Can I also just add that the sweet baked confection shown is a gateau, not a cake. Gateaus tend to have more than one layer of filling, usually a combination of buttercream icing and a fruit jam or compote. The main construction is formed of a light sponge.

Son of an electrician and a

[PBnFlash]

I'm not normally down with the goofy tangents and memes in dry educational videos but you ride the line.

[fredinit]

Jon - You don't have to eat the full slice of black forest cake. The real world is analog - you can have have a 1/2 slice... 1/4 slice... or just grab the cherry from the top. As always, a great video on a very complex topic.

[rubenpulles]

As someone who aspires to work as an analog designer this was really encouraging to hear.

[matthewvenn]

Nice analysis. In my view, we can further divide the field into 'needs the best performance' and 'works well enough'. I think for now analog designers have job security for the high performance area. However, I believe that we'll see the growth of automated and AI tools for 'good enough' analog. Especially in the open source field, as it's a lot cheaper to test and develop.

One of the criticisms of open source ASIC tools I've heard is that the older process sizes are not relevant, but in fact they are still very highly regarded by analog engineers for the reasons you outlined in your video.

Additional interesting reading can be found here: "Open-Source and Autonomous Temperature Sensor Generator Verified With 64 Instances in SkyWater 130 nm for Comprehensive Design Space Exploration"

[stevebabiak]

Analog circuit design using discrete devices is an art by itself. Placing an analog circuit onto an integrated circuit is art at the grandmaster level.

[sellicott]

As someone who has *tried* to use the Berkley Analog Generator (BAG) one of the main problems is setting the system up. First it is a python library (built by grad students) with lot's of dependencies, these are not always readily available on the operating systems used to run EDA software (*cough* RHEL 7 *cough*). After that hurdle is cleared, BAG needs a set of base layouts that the software can array copy (for lack of better words) next to each other. These base layouts are necessary to build up larger transistors with the flexibility to meet the design needs. These layouts are difficult to make due to the complicated design rules for current-gen and leading edge processes. Also, the work to build the layouts cannot be shared between processes as they are, in general, quite different from each other.
All this to say, BAG has significant adoption costs associated with it.

[DerekWoolverton]

Just to clarify, there's no metal in the center of the FinFET, that's silicon--an even worse conductor (semi-conductor in fact), which means even more resistance.

[rydplrs]

Working at an analog company we only considered ESD protection the black magic. Most analog design was fairly automated after proper modeling.

Qualifying a new process was very in depth, and there were a few gotcha’s that popped up in the first designs with nearby devices or interconnects but those could be worked in design rules and coded into automated design tools. We would occasionally find a new problem in mature processes, but those learnings were quickly tested for in other processes and proactively prevented.

We weren’t at 7nm, or 32nm, but the analog circuits were always larger geometry then the digital portions even in analog heavy designs.

[lance]

Been part of several chip and board bring-ups. Getting the analog wrong through bad or lacking simulation cost us a lot of time and money.