The best way to start learning Verilog

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There aren't that many fundamental concepts in Verilog Hardware Description Language, but the few there are, we need to know WELL. This video explores some of these fundamental concepts. We look at Combinational Versus Sequential logic and explore the 3 modelling styles in Verilog; Gate Level, Dataflow and Behavioral.

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At 4:02 I don't understand why the data flow is out1 = ((~X&A)&A)|(B&X); isn't the second &A redundant? I would think assign out1 = (~X&A)|(X&B); ? I haven't tried it in a tool so don't know if there is another reason to construct the statement this way. Great Video. Thanks.

ksbs

Can anyone confirm to me that the statement assign out1 = ((~X & A)&A)|(B & X) should be assign out1 = (~X & A)| ( B&X)

kashaarjun

*Visual Electric* 3:20 Why are there 2 ampersands: ((~X&A)&A)?

ayeflippum

Outstanding! I am a Verilog newbie and was bewildered by the different Verilog programming paradigms until I watched this. Thank you.

audiodiwhy

@3:54 Why do you &A twice ? shouldn't it just be (~X&A)|(X&B) ?

sajanjeka

3:17

nice, but this is simpler and does the same thing

```verilog
module mux(a, b, x, out);

input a, b, x;
output out

assign out = x ? b : a;

endmodule
```

zeep-yt

I don't have any background in this subject, but I want to know why, at the data flow level, he used `((~X & A) & A) | (X & B)` and not `(~X & A) | (X & B)`.

emanon

@3:56 Why (~X&A)&A) instead of ~X&A ?

AK-vxdy

Is the example of dataflow level correct here? At around 3:40, isn't it supposed to be: assign out1 = ( (~X&A) | (X&B) ); #newbie here, dont understand why the 1st AND gate is written as (~X&A)&A

alfandosavant

00:01 Verilog coding involves three different layers of abstraction and understanding the difference between combinational and sequential logic is important.
01:59 Modeling in Verilog at the gate level involves instantiating each logic gate independently and connecting them together using wires.
03:46 Behavioral level Verilog code describes circuit behavior at a high abstraction level.
05:40 Multiplexer can be implemented in different ways: gate level, data flow level, and behavioral level.
07:31 Utilize D-type flip-flops for sequential logic
09:14 Blocking and non-blocking assignments have different evaluation and assignment processes.
11:03 Understanding the difference between blocking and non-blocking assignments in Verilog
12:54 Use blocking assignments for combinational logic and non-blocking assignments for sequential logic.

OmarWaelAhmed

Wow what a great video! Thanks for taking the time to put this together!

andrewphillip

Blocking or non-blocking assignments can give you either combinational or sequential logic depending on the sensitivity list of the always block these assignments are included in.

efnr

3:30 ain't an error in that assign?

riperboyxl

How do codes written at these different level of abstractions convert to synthesis in ASIC Design?

Say I write, assign wire = (a&b) | (c&d) ;

I can come up with 3 possible ways to synthesize this:
1) 2 AND, 1 OR gate ( 18 Transistors )
2) 3 NAND gates ( 12 Transistors )
3) AND-OR22 module ( 10 Transistors )

Which one does the code synthesize in this case and how does it make that decision?

rahi