AXI Part 3: AXI-Lite testbench (briefly)

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Hi, I'm Stacey, and in this video I go over the axi tb briefly

First 2 parts:

Github Code:

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Hi mam, i started my carrer few days back, you r sharing your experience that helps me alot. thanks a lot

RandomPlayer
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Stacey, Hi! Where a u? I'm starting learning FPGA's and ordered basys 3 Artix 7 for beginning, what do u think I should to know for Junior FPGA fronted developer? Or could u make video about this topics?

ruslan
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Hello. I try to initialize AXI VDMA core from PL using AXI lite interface. In simulation all is ok, but on hardware i have some problem. When I read registers of AXI VDMA there is always 0 in RDATA. All other signals is ok, like in simulation, but RDATA is always 0... Why?

infinitumluxelectronics
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can u give code for ps with axi interface

nagarajuchakali
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