How the AXI-style ready/valid handshake works

The ready/valid hardware data transfer protocol is simple and ingenious, providing flow control with only two control signals.

The rules are very simple: data transfer only happens on the bus when both "ready" and "valid" are '1' during the same clock cycle. However, it may be tricky to implement this mechanism in VHDL.

Read the full article about the ready/valid handshake on VHDLwhiz:

09:17 ** Challenge: Pipelining with AXI-style ready/valid flow control

To make learning VHDL fun, I've created a coding challenge where you can practice getting the ready/valid handshake right.

In the competition, I provide a module with a self-checking testbench. The module works fine and runs through all the test cases. But the module's operation is complex and should be split over multiple clock cycles to ease timing.

Your task is to convert the example module to a pipelined design that uses three clock cycles instead of one without limiting the throughput. It should still run through the same self-checking testbench.

After one week, I will post a video explaining half of my proposed solution, which should make it easier. Finally, I will reveal my complete solution after two weeks and explain how it works.

If you are viewing this video sometime in the future, the hint and solution videoes will already be waiting for you on the challenge page. You can still join the membership and take the challenge.

Click here to read more about the VHDLwhiz Membership and join:

Here's a direct link to the challenge page in the Membership portal (only accessible for members):

[uqpodvi]

This is a great video. The AXI protocol, in general, is used ubiquitously, but no one ever bothers to dive into it and explain it. They just say, "It works, leave it at that.". But we're engineers, we can never leave it at that.

[mrsmelaniecook]

Thank you so much for this clear explanation.

[etherbladenet]

Hi Jonas, once "valid" is asserted it must remain asserted until the handshake occurs.

[khaaaled]

Thanks for the video and article, very well put, in an attempt to better understand these things I created a little project with something similar to what you have here, three modules, one reads data from a file and generates a stream, one receives the data calculates the square then streams it to the third which receives it and writes it into a file, my issue is that I don't know if what I have works as an AXI protocol or not, I have a testbench, I can see that the received data is the square of the generated data but everything is delayed by one clock cycle, does that mean I have made a mistake in implementing the AXI protocole? I guess a more speceific question would be this, does the first module (AXI Stream Source) only send data when the final module (sink) is ready, and the in between module (Multiplier) is just a mediator

[yuwuxiong]

When exactly the sending data (in green boxes) are sampled by the receiver (suppose both valid and ready are asserted)? If the receiver uses DFF to register the incoming data, I guess the sampling time is at the raising edge of the clock, which is located at the "tail" of the green boxes. In this case, the setup time (for the receiver) is long enough, while the hold time might be a concern. The wavedrom diagram always draws the green boxes a bit offset (to the right direction) of the corresponding clock cycle, probably considering the Tcd and Tpd of the sender. This offset gives a bit room for hold time for the receiver, I guess.

[joshuanuka]

Is it possible for D1 to be sent before D0?

[ranjeetkumar]

Hellow sir, I am from india and I really enjoy the ready valid handshake data transfer scheme for AXI/AMBA Protocol .but will u please explain this in using verikog and system verikohl please

[brianwang]

You look 23 years old in this video, congratulations. 😄