What is AXI (Part 1)

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In this video I give a brief overview of the AXI protocol.

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Short, concise and straight to the point. Thank you so much, you're a life saver!

yaranaser

Gotta say, I like this style. Simple, clear and direct.
Also commenting to let the algorithm be aware that this video is good

aienbalosaienbalos

Great explanation of not only the HOWs but also for the WHYs of the AXI-Lit bus protocol

christianngameni

Great explanation! First building the right intuition and then explaining the concept helped me digest the content easily.

naman-sharma

This is it! Thank you very much sir for clear yet short explanation

urvashimota

You r targeting a small minority group in engineering sector which is hardware... Still 7k views is a big in this sector... I found this video after 1 year of upload.. feeling good at least now.. great work...

muralikunapureddy

This is beautiful. I had a lot of confusion about buses in the first few years of my undergrad. Then I figured out this way (BRAM interface, how to generalize it, AXI stream and AXI) and this is how I teach it. Just found your channel. Will be sharing this with my students.

AbarajithanGnaneswaran

This is very a clear and intuitive explanation! Thank you so much!

apprentice

short, clear, and easy to understand. thank you very much.

peterxiau

Thank you, Mr. Huff. You explain things very clearly.

duanebarry

Very nice explanation, pls continue making these good videos! Thx:)

marked

Hi Dillon,
Video is very informative and your explanation is very good and it helps to understand the protocol very well. Very good job. Keep making videos like this.

harisharyan

Great overview! Could you do one on AXI in the context of FPGAs?

merrickryman

thank you for the videos and series. it is far more helpful

mohamednady

love it! your style is the best. can i keep you in my library? 😂

RandomHubbb

Very clear knowledge break down! Thank you for sharing these lectures!

kellyyu

Please make a playlist on APB protocol as well

gauravtoshniwal

Hi Dillon, thank you for the video. Nice and clear. Can I get access to subsequent videos?

santoshshetty

6:00 - SRAM Interface
6:10 - read_data has read succeded signal (as it's in the same dirrection); write_responce is opposite of write_data so it has its own channel.

coolwinder

Oh god, at last an engineer who can explain things.

shevechron

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