Master AXI protocol: AXI WRITE 1 Byte length

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By keeping the length constant, you can observe the impact of AWADDR on WSTRB, and gain a deeper understanding of how these two parameters interact during the execution of an AXI transaction.

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Автор

Hi, if the transfer size is 1B for a burst of length 4 and data bus is 4B. What will be the addresses of each transfer? Will it be incremental by 4B or 1B ?

shilpimishra
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Thanks for covering this topic !

One approach shown in the video is to control the address and WSTR both.
Can the same result be achieved by keeping the address the same and only changing the strobes?
Eg :
The naturally aligned address will be 0x0, 0x4, 0x8....

ADDR - 0x1000 AWLEN - 0 WSTR 0x1 -> Update the slave memory with byte location 0 (Addr 1000)
ADDR - 0x1000 AWLEN - 0 WSTR 0x2-> Update the slave memory with byte location 1 (Addr 1001)
ADDR - 0x1000 AWLEN - 0 WSTR 0x4-> Update the slave memory with byte location 2 (Addr 1002)
ADDR - 0x1000 AWLEN - 0 WSTR 0x8-> Update the slave memory with byte location 3 (Addr 1003)

writetorohit