Introduction to Axi Architecture || Amba Axi Bus protocol

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Комментарии
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In the first step, should the sender wait for the ready signal? If it does, wouldn't there be a deadlock? The sender waits for the receiver's ready to raise valid, and the receiver waits for the vaid to raise ready? I think to prevent deadlock, valid and ready cannot depend on each other. If the sender raises valid but receiver is not ready, the sender should simply hold the data and wait.

brucesdx
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Sir, initialy you saying read address channel send the address from slave to master but in the diagram read address channel the address send from master to slave .
Which one is correct?

poojarianilkumar
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SIr, can we get the ppt link for this tutorial? It would be a great help

shivamdwivedi
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Sir is there tutorial for verilog rtl for axi? If yes then please share link

krutikakhakhar
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you need to work on your explaining skill

MSQ