PD Lec 27 - Sanity Checks -2 | Floor-planning | VLSI | Physical Design

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This is a 27th video on sanity checks in Floorplan in VLSI.
In this video, we discuss about different sanity checks in floorplanning in design. Specifically SDC related checks

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Комментарии
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before floorplan any sanity checks is needed

ashokkumarm
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PnR and CTS has not done yet then how can we check timing (Clk)related issues

radheshyamshaw
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could you please give an examples to unconstrained endpoints

Siva-rzxj
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Can we force Input transition and output capacitance on all the ip and op cells?, because they are the values used to find cell delay in .lib and each cell will have different cell delay

sumanth
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Hi, what is the difference between set_load and set_ouput_delay ?

praveen
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what is the importance of multiple clk ips

ramojiraobheemavarapu