VHDL vs. Verilog - Which Language Is Better for FPGA

Finally an answer to the age-old question! VHDL vs. Verilog for FPGA. Who will be the champion in the most heated battle between the Hardware Description Languages. Find out now.

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[shwetasharma]

I have recently came across your channel and i would say every video is very informative and practical too.thank you for sharing your knowledge and looking forward for more FPGA videos .

[salmankhan-ywoc]

Thank you so much for putting this video. And it feels like knowing one language is enough for a fresher.

[hmdz]

As a long time C programmer I have an easier time doing HDL coding using VHDL. Coding HDL requires a totally different mindset compared to coding software. That is why Verilog is confusing for me. It doesn't let me think free from software mindset.

[tinori]

I really liked how you showed pros and cons for both and i like your conclusion. When it comes to programming languages a lot of people are pretty emotional but this was just a very good explanation.

[martinwashington]

Very nice introduction to the difference between the two HDLs, thanks for taking the time present an upload :)

[cosmofic]

It's 7 year old video and I'm watching in in 2024 and starting my journey now . 🙂

[vonnikon]

Verilog is being more actively developed, with new features added first in Verilog and years later in VHDL.
One example in particular: It is possible to represent a databus like AXI as a single port in Verilog. While in VHDL your AXI bus will be 25 individual ports.

This feature is coming to VHDL as well, but it takes years for it to happen...

[DanEllis]

I started learning with Verilog. I think I'll end up switching to VHDL eventually, because strong typing is good. I've already experienced errors that slipped through in Verilog.

[ibrahemtaha]

Many Thanks for sharing your videos bro!!!
Any chance you share with us Paths "How to become X defense engineer".
Thanks in Advance, bro!!!

[bertcuzeau]

Nice intro for beginners. I would just add:
* ASICs are in Verilog (especially close to back-end)
* If Digital Design is going to be your job, then you need BOTH !
* Neither are intuitive nor very simple to learn, HDLs are another breed as compared to programming languages.
Self-teaching HDLs is not a professional nor reliable path.
* AND there is a huge Game Changer now : SystemVerilog which is the language of the next 20 years (if HDL and FPGAs don't die in between).
Since SV is a superset of Verilog, so today I would rather suggest learning Verilog rather than VHDL, even if (being located in Europe) I wrote more VHDL than Verilog since 24 years.
Bert

[burgerking]

My Verilog professor said Verilog was the best and was not bad like that clunky mess of a language VHDL. My VHDL professor said Verilog is an ancient language no one uses

[ldjnpmg]

Dear Sir
Thank you very much for your helpful information.
I want to work a project of tracking of moving target in real-time using FPGA.
What is your advice to me to use VHDL or verilog?
Thank you.

[gmortimer]

I prefer the pedantry of VHDL, which as a beginner constructing a huge project (which occupies 70% of a Zynq 7100) I find somewhat helpful. I can use .v and .sv, though, too. The version of Vivado I use (15.4) sometimes gets confused when I construct a piece of custom IP, and if the piece is simple, and it defaults to .v, then I use it! For anything of substance I use VHDL.

[ashwinikurhade]

Can anyone suggest a good book for Verilog?

[raysful]

I worked in both Silicon Valley (Apple) and defense (Raytheon). In Silicon Valley I did two FPGAs. Very tiny little FPGAs. Both in verilog. In defense I did a whole lot of FPGAs and huge designs. Entire radar processing to controls. All in VHDL. What I learnt was that the use of FPGAs in Silicon Valley is very low compared to defense. The bulk of FPGA work is in defense. I Silicon Valley most products are consumer products and se has to be small and cheap and power efficient. So any FPGA design is quickly made into an ASIC and the work continues in C.

[lawrencemanning]

I use VHDL in my hobby projects. It is certainly much more verbose. I like it for this reason, oddly. But I'm very keen to learn Verilog, especially as I want to do this for a living. One nice aspect is it's apparently possible to mix different languages in the same design, so I'll have a go at rewriting some bits in Verilog. Maybe I'll end up liking it.

[derekonxbox]

3:59 Is there a train passing by? I swear i hear a graham white e-bell ringing and a loud rumble in the background

[agstechnicalsupport]

A good, unbiased comparison of VHDL and Verilog.

[KingDuken]

I think Verilog is a good start for anyone who is starting and just learning any hardware description language. VHDL is more for advanced users who want their code to be more literal and accurate. There's really no "better" language. It really comes down to what you think is easier and what will get the job done according to well thought out specifications.

[vitvit]

VHDL and Verilog are hardware description languages but not sftware programming languages. So they are the congenerous semantics. Hence we make schematic diagram using verbose languages instead graphical representation of a dot. But, easier to say 'horse' then making its drawing. And this case, I suppose, that Verilog and VHDL languages have to draw the same device (spherical horse in vacuum) for all supported FPGAs.