Example Interview Questions for a job in FPGA, VHDL, Verilog

[jordanhardy]

Thanks Doug Demuro of Embedded Systems

[matthewllarena]

"Pretend like you're interviewing with me for your job, pause the video, give your answer to me. I'm not going to hear it obviously, we're not there yet with the internet but.. maybe some day". Haha, looks like we're at that day

[joer]

80% of the questions we covered in the last month and a half (sophomore year) in EE! Thanks for giving us the insight on what to look for and to keep on the tip of the tongue

[kdjohnson]

Appreciate the video. I had an interview for digital design (with spacex) even though I'm a computer engineer. The questions that got me are the following:
how do do know cdc data is ready when using dpram?
explain some timing constraint experience
how familiar are you with making build scripts (in vivado, libero, quartus, etc.)
explain a fpga design you have been the lead of (schematic, worst case analysis, timing analysis, embedded c, etc.)


just wanted to give you an idea of what I see in the modern workspace. I always send co-ops to your videos. keep up the good work!

[varunnagpal]

This is really nice. Good questions and I learned new things today.


But At 7:50. Are you sure DRAM is faster than SRAM ?


1. SRAM uses multiple CMOS transistors to store a bit(typically 6-8 CMOS FET's) while DRAM is made up uses single transistor plus a capacitor. So memory cell of SRAM occupies more area than memory cell of DRAM. DRAM is thus more dense and can fit more memory bits in same areas as SRAM cell.
2. However, DRAM needs to periodically refresh (hence dynamic and not continuous power supply) the charge on the capacitors of its memory cell which tends to leak with time while SRAM cells remember their logic due to cross-coupling(feedback) and continuous power supply from VDD/VSS power rails (which makes it power hungry).
3. Data can be read from SRAM at lower latency (order or more) and higher bandwidth (several orders) compared to DRAM. So SRAMs are faster than DRAM.
4. SRAM is used for very small (KB to few MB) fast on-chip L1/L2/L3 instruction and data caches on cpu's/gpus or or scratch pad memory in embedded socs while DRAM (GBs to TB) is used off chip to store high amounts of data.
5. SRAM per bit is more expensive in terms of area, power, and money compared to DRAM so SRAM is only used in small sizes (on chip or off chip) and to store data whose access time is critical to speed.DRAM us used when higher capacity is needed but speed of access is not important.

[muhammadkhan]

They literally asked questions straight from here and I got the internship position. Thank you so much!

[turkishjedi]

Using this to study for an RTL design internship interview in 2 days. Ever since I started watching your videos 5 months ago, I've fallen in love with FPGA design. Thanks for all you have done for me!

[chrism]

"Melee machine!" HAHA, that's a good laugh. It's "Mealy", "melee" is a fight.

[jackyzou]

DRAM is not faster than SRAM because DRAM requires constant refresh to retain data and CPU cannot retrieve data from DRAM while it is being refreshed. In contrast, SRAM, since it's static, it can be accessed anytime without waiting. And because of the smaller size of SRAM, walking through the cache pages is much faster than the bigger DRAM.

[eveHabanaro]

I think the questions are reasonable, some answers are fine, but not all. Some answers are wrong enough to give you a bad outcome in an interview. Here are some corrections:

q3: diff flop latch
A better answer is the difference has to do with how the output gets updated. When a latch is open it is 'transparent.' Changes on the input D show up on the output Q (after some tprop). In a flop the output does not change until the flop is clocked. So changes on the input before the clock are not visible on Q. When a latch closes D will no longer effect Q, until the latch opens again.


q4 choose an fpga
FPGA's are _always_ slower and bigger than an equivalent std. cell design. It is fundamental to how FPGAs provide the re-programmable feature. E.g. a 14nm FPGA will achieve ~+500MHz in logic/processors, a 14nm std. cell design will achieve ~++2GHz, all other things being equal. This is because FPGAs implement some logic indirectly (luts, muxes, etc.) while std. cell designs implement logic directly (nand, nor, etc). This speed difference is the reason FPGAs have to provide hardened DSP blocks and the like to mitigate the performance degradation.

The main points are: ASIC/std cell's are costly to manufacture, can not be changed without re-manufacture while FPGAs have a better cost model, can be iteratively designed and can be modified even in the field.

i/o has nothing to do with fpga vs std. cell.
high mem b/w requirements have nothing to do with fpga vs std cell
tons of math operations, these are always as fast or faster, smaller, less power in a std cell design
all the applications you mention are easier to implement in a std cell design than FPGA.


q6 diff between sram dram
You should skip this answer completely and go find your own. If you gave me this answer it tells me the candidate does not understand the difference.

There is a difference between access time and bandwidth. DRAM is not faster than SRAM, do you see any cache tags or TLB's built from DRAM? Nope, all SRAM. All things being equal SRAM has more available bandwidth than DRAM due to refresh overhead and due to the row activation, column activation semantic required by the multiplexed address pins of DRAM.

DRAM bit cells are fundamentally smaller (3 or 4T cells) than an SRAM bit cell (6 or 7T cells). That is why you need to refresh DRAM, it's charge will degrade, not SRAM. 3/4T makes DRAM great for bulk RAM.


q9 what is meta-stability
Again, good question but go find another source for the answer, using this answer will not help you.

Anytime you violate the setup and or hold time of a flip flop you risk putting the flop output into a meta-stable state, i.e. it is not reliably a logic 0 or a logic 1. The flop's physical design determines how long it takes for the flop to stabilize.

The signal source, internal or external, has nothing to do with the likelihood of inducing meta-stability. If the signal is asynchronous to the clock used by your flop there is a probability of inducing meta-stability.

The risk of meta-stability is statistical, the more asynchronous the driving clock to the capture clock the more the risk of meta-stability. This is the reason dual flops are used to capture source asynchronous signals, including those crossing a clock domain. The dual flops reduce the probability of a meta-stable event to near infinitesimal.

q16 clock crossing
Fast vs slow is not the issue. Two clocks of the same frequency but not synchronously related still require meta-stable filtering techniques.

q18 melee(sic) vs moore
This is text book stuff, good question for junior people, if you are one you should have this exactly memorized:
Mealy: outputs determined by current state and current inputs.
Moore: outputs determined only by current state

[pfrankis]

I was always taught that the difference between Moore and Mealy was not about what state to go to next but more about the outputs at each state. In Mealy, the outputs are dependent on the current state and the inputs, but in Moore the outputs are only dependent on the current state only.

[diamoncoat]

I think that
SRAM is faster than DRAM, and both flip flop and latch can have clock, the difference between them is that the output flip flop happens when the clock is going up or going down, meaning in the transition from up to down or from down to up ( 0 to 1 or 1 to 0 ) however in latch the output happens when the clock is up or down depending on the design of the latch

[krunch]

I graduated recently and decided I wanted to work with fpgas after some experience with them during an internship, just after applying for a graduate role I watched this video and used your site to prepare for the interview and I'm happy to say it paid off and I got the job! Thank you very much for helping me achieve my goal of becoming an fpga engineer

[string]

As someone who got into FPGAs just a few days ago, I can confidently say I will not be getting the job

[ishwarbannur]

I believe that Sram are much faster than SDRAM, nad main difference is that Dram is much more volatile than Sram so we need to refresh periodically but in sram its automatically refreshed as there is crossed couple inverters pull the data continuously with out recharging, and can also diffrentiated by the construction of these memory

[begodcod]

Mixed up things a little while talking about mealy and moore state machines. It's the output which depend either on the state and the input (Mealy) or only on the state (Moore). You were talking about state transitions, which depend on both variants on state and input. Maybe add a comment to the video to not confuse some newbies watching :-)

Besides, great video! :-) Liked it.

[varunrain]

I recently landed a job as an FPGA engineer. They asked pretty much the basics. However, I wasn't able to answer a couple of them. Could you help me with that?

1. Using IPs(microblaze), HDL wrapping and writing C programs using the Xilinx SDK vs Doing everything using VHDL from scratch to finish - Which method is more efficient in terms of timing, area, and resources?

2. Simulation looks good, synthesis and implementation look good, a bitstream is generated and FPGA is programmed. However, the FPGA doesn't function as per requirements. How do you go about debugging starting with your bitstream?

I think these two questions are critical.

[fernandoi]

4:00 A melee machine beats the hell out of you lol

[timdipayanmazumdar]

I have been writing Verilog Code since at least 1994. I finished my MSEE in 1990. I have now been coding Verilog and Matlab for almost 30 years. Its very good that you made this Video. Good questions too. I wish you add more content - one common area would be

1. Clock domain crossings - in Verilog.
2. FIFO design with Grey coded counters in Verilog - Cliff Cummings - 1994
3. AXI-4 streaming Interface - which requires 4 signals.
4. AXI-4 Slave design.

[duanhaoming]

I think the answer for the difference of latch and ff is ff is triggered by edges of signals, and latch is triggered by signals.