Digital Design & Comp Arch - Lecture 7: Von Neumann Model & Instruction Set Architectures

Lecture 7: Von Neumann Model & Instruction Set Architectures
Date: March 16, 2023

01:43 Timing and Verification
04:01 Timing in a Single Sequential Component
14:20 Make Sure a Design Works Correctly
26:43 The von Neumann Model & Instruction Set Architecture
29:35 Building a Computing System
32:30 The von Neumann Model
36:15 Memory
38:50 Word Addressable Memory
40:59 Byte Addressable Memory
43:34 Big Endian vs. Little Endian
46:45 Addressing Memory: MAR and MDR
50:05 Break
1:01:50 Processing Unit
1:05:53 Processing Unit: Fast Temporary Storage
1:11:46 MIPS Register File (Conventions)
1:14:19 Control Unit
1:23:18 LC-3: A von Neumann Machine

Recommended Reading:
====================
Intelligent Architectures for Intelligent Computing Systems

A Modern Primer on Processing in Memory

RowHammer: A Retrospective

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[paulbird]

01:43 Timing and Verification
04:01 Timing in a Single Sequential Component
14:20 Make Sure a Design Works Correctly
26:43 The von Neumann Model & Instruction Set Architecture
29:35 Building a Computing System
32:30 The von Neumann Model
36:15 Memory
38:50 Word Addressable Memory
40:59 Byte Addressable Memory
43:34 Big Endian vs. Little Endian
46:45 Addressing Memory: MAR and MDR
50:05 Break
1:01:50 Processing Unit
1:05:53 Processing Unit: Fast Temporary Storage
1:11:46 MIPS Register File (Conventions)
1:14:19 Control Unit
1:23:18 LC-3: A von Neumann Machine
1:29:36 Stored Program & Sequential Execution
1:30:38 A Sample Program Stored in Memory
1:31:47 The Instruction
1:33:51 Instruction Types

To be completed

[RishikeshS-nvol]

A wonderful lecture! Thank you for making this freely accessible

[aneeshjoseph]

Professor Mutlu - I love your lectures. I wish I was able to attend your class during my undergraduate studies. Your students are very lucky indeed. :)