Digital Design and Comp. Arch. - Lecture 16: Superscalar Execution & Branch Prediction (Spring 2023)

Lecture 16a: Dataflow & Superscalar Execution
Lecture 16b: Branch Prediction
Date: April 27, 2023

Recommended Reading:
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Intelligent Architectures for Intelligent Computing Systems

A Modern Primer on Processing in Memory

RowHammer: A Retrospective

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Rethinking Memory System Design Lecture @stanfordonline :

[AshutoshMishra_Umich]

I have a quick question. Lets say we have instructions like:
...
bne r1 $0 loop
sw r2 0(r1)
...
Lets say we go ahead with the taken path, i.e., execute sw instruction after bne assuming branch is Not Taken. On a branch mis prediciton (bne actually turns out to be Not Taken), how do we update the memory with correct value because sw was not supposed to be executed and change the values in memory. I am asking this question with respect to both a R10K/P6 OOO core and a simple 5 stage pipeline core.