Digital Design and Comp. Arch. - L17: Single-Cycle Microarchitecture II (Spring 2024)

Lecture 17: Single-Cycle Microarchitecture II
Lecturer: Frank Gurkaynak and Mohammad Sadrosadati
Date: April 26, 2024

Lecture 17: MIPS Assembly II

Recommended Reading:
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Intelligent Architectures for Intelligent Computing Systems

A Modern Primer on Processing in Memory

RowHammer: A Retrospective

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Memory-Centric Computing Systems Tutorial at IEDM 2021:

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Computer Architecture at Carnegie Mellon Spring 2015 Lectures Playlist:

Rethinking Memory System Design Lecture @stanfordonline :

[mr.morgans]

26:02 you said about being able to use the 16 bits in the immediate of I-type instruction as 24 bits How is that possible?
even adding base (rs) you get 5+16= 21 bits. if it is something like using the Program Counter (PC) relative? but then you have PC be 4, rs be 5 giving 4+5+16 = 25 bits ???