Digital Design and Computer Architecture - Lecture 15: Out-of-Order Execution (Spring 2023)

Lecture 15: Out-of-Order Execution
Date: April 21, 2023

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Intelligent Architectures for Intelligent Computing Systems

A Modern Primer on Processing in Memory

RowHammer: A Retrospective

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Rethinking Memory System Design Lecture @stanfordonline :

[mikafoxx]

It's incredible that Robert Tomasulo came up with out-of-order execution and used in 1967 in the IBM 360/91, and then it was slept on for another decade or two until frequency scaling feom die shrinks wasnt enough, and you had enough transistors to make it. Much like the old 360/91. Slow clock but lots of transistors available..

[arifnishan]

What i learn: In out-of-order execution, instructions are not executed in the order in which they appear in the program or code sequence. Instead, the processor dynamically reorders and schedules instructions based on the availability of execution resources and the resolution of dependencies between instructions.

[АлишерХасен-кю]

Didn't get, in hardware can we execute two instructions simultaneously? I am talking about stage after decode, I think we don't have a lot hardware to execute simultaneously?
like two multiple or two adds ?

[Abhishekkumar-qjhb]

@27.14 video the comparison of in-order vs out of order a minor error that needs modifcation: the MUL uses 4 cycles in first instruction and 5 cycle in fourth instruction so that is wrong, it should be 15 cycles vs 12 cycle, overall 3 cycle improvement, so please correct it in future lectures

[АлишерХасен-кю]

how are you broadcasting simultaneously two finished execution?

[Rehan-Naeem]

I slide 36, no. of execute cycles for MUL instuction is 8 not 6.

[chenyangzhou]

Hello, can I ask why we need the architectural register file and when to update it, just after retirement?

[secondclone]

In slide 82, 'getting rid of replicated values 2'. In both RSs there are an additional V column compares to the 2022 version. You says they are for values, but I couldn't figure out what they are for. Can you please elaborate on that?
Also, at decode/rename does 'allocate dest pr to dest reg' mean 'copy the physical register pointer of the current instruction destination to reservation station for broadcast after it complete'?

[АлишерХасен-кю]

And out of order execution 
we are literally changing order
what about previous concepts of von Neiman from prev lecture, that each instruction should be after another without changing order? 
That it's hard to debug, we have some error, like division on 0, and when debugging we think that some instruction that after some potential errors instruction not executed but in real they already executed

[GoatMen]

How is it that my university in the US has professors that can hardy speak English but Zurich has professors with better English than Shakespeare?

[АлишерХасен-кю]

how in one cycle you are executing two adds?