PD Lec 35 - Scan Chain Optimization | VLSI | Physical Design

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This is a 34th video on place-opt in Design in VLSI spectrum.
Please ask your doubts in comments.

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Thank you for your detailed explanation about scan chain ordering 👍 now it clear all my doubts

bmallu

Your videos are really productive and helps in making concept clear. Thank you so much for your efforts. 🙏

nehapandey

I guess scan chain reordering and scandef as an input to placement need to emphasized clearly. Also the initial comment of only a limited scan flops in a design could leave anyone with an idea that many flops are not scannable. That's not the case is current designs. Almost all flops are scannable

vandi

Sir plzz increase the frequency of the videos..plz sirr

BP-pfuk

simple and excellent explanation
want more info on CTS stage
keep doing sir.
if possible please avoid the background music

kalyansai

Sir one doubt.
If end cap cells are used to prevent manufacturing defects then why even go with scan chain inputs for checking if manufacturing defect was present or not..

Narennmallya

Sir can you explain about the scan violations and fixing methods

tirlangikulasekhar

test signal not go in the combinational path how will you check combinational path defect ?

nnc

Hi sir your videos are very useful for learning the concepts easily, can u pls upload synthesis flow.

balakrishnan

Is it valid, if I see sin pin at input at FF in functional mode?

raveenasaldana

what happens to scan chain if we do banking or debanking of flops in place stage? Kindy throw some light on this aspect.

dhogalevivek

scannable flops are flops present in one particular high fanout path.... these differ from normal flops as they have that additional mux that chooses test/func mode. This is given by DFT people..am I correct until here? .so my doubt basically is only flops present in scan chain have that extra mux logic? and there is only one such scannable path per design?

saidileepchowdarynuthalapa

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