What is a Block RAM in an FPGA?

How Block RAM (BRAM) works inside of an FPGA for beginners. Learn about when and where you would use BRAM. Learn about different configurations: Single Port, Dual Port, FIFO. How are Block RAMs useful in crossing clock domains.

Shows how to instantiate, infer, and create BRAMs via the Interactive GUI, used in both VHDL and Verilog.

Like my content? Help me make more at Patreon!

[jacobseal]

Nice explanation. Just ordered the go board yesterday. Can't wait to get started.

[Gruftgrabbler]

I am learning BlueSpec and have to do a exercise where I need Block Ram. I had no idea what this is so thank you for this video :)

[k.wonderwei]

thank you for your tutorial. I'm desperately looking for an example or tutorial for block RAM instantiation. do you have one please? Thanks

[muhammedfayas]

Hello Sir, can you please make a video how to store the text file in block RAM.

[kaypope]

Awesome video! Thanks for explaining on BRAM in detail.

[lidar]

Hi Russel

Could you please create some BRAM examples on EDAplayground that could then be migrated to the GOboard.

[ahmadmaihreze]

thank you it was usful, i wait for more details of other components in FPGA, thanks

[Dhaif_El-Jaber]

thank you for your help i understand verlog from your channel just

[kedharguhan]

I am not able to wrap my head around what exactly makes, a BRAM. Since BRAM has variable width and depth, does it mean each and every bit of it is independent and addressable?

[MITESHSINGHRAJPUROHIT]

can provide info about how to store pixel of a pic into bRAM

[Andrew-egpc]

Is there any FPGA verilog example of reading and writing BRAM?

[wisnueepis]

Could you give an instance to initialize the bram module on new blank verilog project. So, i could store some data in it. Thanks bro

[varunrain]

Hi Russel,


Could you tell me how to write a testbench for a BRAM of depth 50. I mean if the address we use for BRAM, Ex: bram(addr1) is more than 50 in terms of depth, how do you provide a 50-length long value for it in the testbench?


Thanks,
Varun

[yukeyang]

Thanks for your video, but I don't really understand the first two ways of generating a BRAM at around 12:39.It would be much better if you can describe it using some more specific instances, such as code snippets or showcasing it yourself. Still, this is an awesome video, best regards from China.

[JL-xuvq]

Hello I like your videos, could you put a link of the power point of the video to let download it please?

[phillipneal]

Hi ! I am working on a program where I use your UART_RX and UART_TX to write back and forth to my MAC. But I want to save state on the fpga between reads and writes. For example, to calculate the sum of numbers arriving on the UART_RX then send the sum back to the MAC on the UART_TX. Can I put the "sum" variable in bram and still maintain state ?

[nandithanvarma]

That was very informative..Sir I have a doubt.. Suppose Ihave a textfile and wanted to take its contents and store in this Block Ram.. is that possible?

[Sarth_draws]

why do you want 1 << addr_width in the memory you have taken. why 1 is left shifted
in reg[datawidth - 1:0] mem[ (1 << addrwidth) - 1:0];

[hyemimin]

Thanks for the video, I have a question.
You mentioned at the end of video, BRAM is not recommended for large design.. then what is another option for large design?

[노영욱-qy]

I have one question. If I made '8bits width' and '1024 depth' BRAM, than whole size of memory that I made is 8*1024bits??