Intel’s Next Breakthrough: Backside Power Delivery

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[tvm]

As an imec researcher I’m seriously impressed by how you made a complex topic easier to comprehend for a layperson. I should learn your techniques when I talk to my bosses 😂. Bravo!!👏

[AlexSchendel]

Backside Power Delivery Network is actually known as BSPDN in the industry. Also, while Imec does incredible research for the industry, the research into BSPDN is a bit nuanced. As you noted, Imec relies on BPR (Buried Power Rail). While this is significantly simpler to manufacture, it provides much less in terms of gains as it requires more space in the cell and still takes up valuable M0 routing space. This also harms voltage droop somewhat.
Intel's PowerVia goes with a different approach where the TSVs attach directly to the transistor contacts which means they do not need to rely on BPRs which take up die space and they also do not need to rely on any M0 routing for power at all. It is a more complicated manufacturing method, but it provides much better scaling. Lastly, it is believed that TSMC is attempting to connect TSVs directly to the source and drain of the transistors with its implementation of BSPDN. This provides even greater density, but takes the manufacturing complexity to another level. This is believed to be a big part of the reason why TSMC has delayed their intro into BSPDN... Semiengineering has a nice article about this topic. It is from 2022 though.

[DigitalJedi]

I made a similar comment to this on the video by High Yield about this, but hi! I worked on this. I've been with Intel for nearly a decade and have participated in the bring up of Intel7, Intel4, 20A, and am currently on a next-gen node that can't be named here yet.

I did my PhD in semiconductor physics while at Intel, partially sponsored by them, completing in early 2020. I studied the optimization of chip-to-chip power delivery, such as you see with a silicon interposer passing power through to dies on top.

Between this video and his, you can get a great overview of these technologies and the sources mentioned at the beginning are some of the best out right now. I'll answer what questions I can here, but I highly recommend taking a peak at my comment on the High Yield video, as I'm well over 100 replies deep in Q&A there.

[glennac]

Wow Jon. I’m impressed with how your channel has attracted comments and participation from the folks actually doing the research and development of these topics. Fascinating reading long after your video has ended. Bravo❣️👏🏼

[maybehuman]

It's sad that while hardware keeps getting faster and better, the software that is run on it keeps getting more bloated and slower.

[HighYield]

Waiting at the airport for my flight to Computex and watching a Asianometry video. Can life get any better?

[bradsalz]

Back in 1985, as a new IC process engineer working for AT&T in their Orlando, FL, CMOS fab, I tried an experiment just for fun (fun being a relative concept) where I thinned a silicon wafer with a Disco backgrinder with increasingly finer grit grinding wheels until the wafer was less than 3 mils thick - approximately the thickness of a piece of paper. Upon releasing the wafer from the vacuum chuck I noticed that the wafer would deform into the shape of a potato chip and would often fracture under the immense stresses introduced by the grinding process. Although the video doesn't adress this issue, I have to assume there is an annealing step included in the procedure used to thin out the wafer not mentioned, else this would not work.

[Theoryofcatsndogs]

Jeff, you should be ashamed of yourself!

[qijq]

Great video, Asianometry! I learned a lot with this video. You touched briefly on this when discussing standard cell geometry, but moving the power to the back of the wafer will also drastically reduce signal routing congestion thus allowing for more transistors per unit area.

[AKKI]

Is this really a new breakthrough? I've been backsided by Intel for two decades at this point

[gregebert]

Intel has done TSV (thru-silicon Vias) in the past with FOVEROS. That was for signals, but I'm certain the learnings from that paved the way for backside power delivery.

As the video points out, there are so many metal layers that power delivery is interfering with signal routing, so the motivation for backside power delivery is clear. For ground, it's probably a trivial procedure because the base silicon is a P-type substrate, which is ground, so a "short" between a VSS TSV and substrate is meaningless. Actually, it's probably desirable. I think the challenge is for power, because the TSV's must NOT make any electrical connection to the P substrate, otherwise it's an electrical short.

It's relatively easy for manufacturing test to find failed (either shorted or open) TSV connections for signals, because those failures will prevent signals from going-in, or coming out. But for power delivery, I dont know how you can find individual opens because multiple power pins and buses are grouped together.

[jacobscrackers]

Thanks for not making a single joke about backsides. I know that took restraint.

[middle_pickup]

The more I watch your videos the more I realize how chip design is the coolest geometry problem ever.

[OrenTirosh]

It’s ridiculous how little of the original wafer is left…

[yoav]

@4:39 i believe it should be bypass capacitors. bypass capacitors are used for quick energy supply (power source bypass) and decoupling capacitors are used for line regulation (noise from a submodule should be decoupled from the rest). although in most application they are treated as the same thing.

[ljwljw]

Just WOW. The first time I watch your tech video and it just blow me away. Hardcore social topics, history as well as hard tech. This channel is a treasure for all curious minds!

[szurketaltos]

Ah, so old CMOS before backside wiring would be like if blood vessels were directly in front of the retina.

[Drew_TheRoadLessTraveled]

I enjoy the way you explain in-depth topics in a way anyone can understand without feeling like a dork. I often enjoy the sledge hammer humour for those in the know...
You have become my favourite lecturer of all time... I don't even have too get out of bed too learn something. Hehe.

[royjones]

Thanks again, always appreciate the work that must go into delivering such high quality content

[TheRealEtaoinShrdlu]

"Backside Power Delivery"

Is that like the sun shining out of my butt or something?