AP Power Sequence Subsystem - Bernardo Salvador Perez Priego, Intel Corporation

AP Power Sequence Subsystem - Bernardo Salvador Perez Priego, Intel Corporation

This talk introduces a subsystem API in Zephyr to manage the ACPI power sleep states of a connected application processor (AP). Users of this API will be able to query and receive notifications upon AP power state transitions. The AP power sequence subsystem is built on Zephyr's State Machine Framework (SMF), providing flexibility for AP architecture, chipset, and application specific requirements. ACPI’s global state (G3) and its six sleep power states (S0, S1, S2, S3, S4, S5) are present within the state machine domain. All these ACPI states have three hierarchical levels: - Architecture: is the highest level of the hierarchy, SMF states at this level perform operations that are shared by all designs based on a specific AP CPU architecture. - Chipset: these SMF states drive the power of components and monitor power good signals that are required for a specific AP chipset. - Application: is the bottom level of the hierarchy and these SMF states are reserved for action handlers intended to address platform or application specific computations. Utility macros and functions are also provided to easily follow hierarchy early described. Allowing implementation to register state action handlers, and safely perform state transitions.