Verilog Interview Questions #verilog #vlsi #semiconductor #digitalelectronics #cmos

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here fork and join would run the process in parallel manner so At 20 ns time period data will be reflected in b as 1, while At 30 ns a will latch the data as 1.

jogeshsingh
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Since it need to wait for 10 time units for positive edge of clk, fork block will start execution after 10 time units and then at 30 time units b will be 1 and at 40 time units a will be 1.since there is no value assignment for a and b at negative edge of clock, a will be having value of 1 after 40 time units and b will be having 1 after 30 time units.so altogether a = 0 till 40 time units and a = 1 after that and b = 0 till 30 time units and b = 1 after that.

vijith
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before 20 ns a=0, b=0
At 20ns b=1 a=0
At 30 ns b=1 a=1

MukeshKumar-vhzp
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