Latest VLSI Interview Questions #verilog #systemverilog #uvm #cmos

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Since reg can hold value, it not be driven continuously by a source so there is no significance of “assign”

bharadwaj
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assign reg_a=1 is wrong
assign statement is used only for continuous assignment
reg_a is procedural assignment

EngineerslibraryAkashBose
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It may be reg_a=1 or it is illegal assignment

noorshaikh
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