HOLD TIME CAN BE NEGATIVE!!! | STA-3 | Static Timing Analysis

Hello,

Welcome to The Rising Edge!

I am Yash and this is the third part of Static Timing Analysis.

In this video, you'll get the answer to a very popular question asked by interviewers, which is about the Negative Hold Time.

Stay tuned for the complete series, keep learning, and All the Best for your placement preparation.

#STA #Negative #Hold #StaticTimingAnalysis #SetupViolation #HoldViolation #SetupAndHoldTimes #FlipFlop #DigitalElectronics #PlacementPreparation

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[sailajapeddakotla]

You know how many pauses that i've to take to get the whole thing completely into my brain but its totally worth investing time in this playlist...🤩

[saradarandomworld]

just wow, what a beautiful explanation, best explanation, actually for this topic very less, lengthy and bearing videos are available in youtube . you just made it simple and detailed it in a small video, thank you bro

[anjaliagrawal]

I was asked regarding Negative Hold time in my interview. You have provided a good explanation of the topic. Thank you 😁

[sreekantasai]

Delay of Transmission gate Tg=5ns doesnt mean it will be turned off after 5ns. It will turn off based on clk whether clk is pos or negitive. Delay Tg=5ns means o/p will be delayed version of i/p by 5ns

[velugubantlapriyanka]

In case 3 where you considered Tin as 7ns which means the setup time is increased by +7ns and data should arrive at D pin 7ns+extra setup time prior for it to be captured correctly so definetely negative hold times impose a threat to setup timing making it hard to fix

[dhamusundaravadivelu]

good explanation. i am not sure if there is already a comment about this and please correct me if i am wrong, theoritically library setup time of a flop cell can also be negative, if the datapath delay < clock path delay in the internal structure of the flop.

[ghanshu]

Beautifully explained, Thanks a lot !

[nagendraprasad]

fixing the hold violation then followed by setup violations would probably ensure that they are fixed for both ends

[pavan_pelleti]

🙏🙏🙏 The best...your clarity and quality is SUPERB....but i request you to do more playlists regarding digital electronics, verilog, vlsi

[ansariaburehan]

Thanj you brother ❤.. make more videos like this

[gauravkaushal]

great video,
now because of the Tin delay will the setup time also increase by 7ns? Since now an additional 7ns is also needed for the data to reach the first gate.
so if before it was 1ns then will it now be 8ns?

[shreyakumari]

It will help students a lot!! Very nice job!

[prabhasiva]

When there setup time is negative the will be effected or not can please tell?

[prashantsharma]

Hi Yash, thanks for the explanation.
In case 3, where hold time is negative, then what will be the setup time for flip flop? will it be any time b/w 0 to 5 nsec.

[sattwikghatak]

brilliant video presentation and editing as well as explanation, very rarely seen content quality

[chaitanyab]

Setup time is not always positive, it can also be negative

[uday]

Nice explanation. Thank you very much 👍

[NAGENDRAARASANK-ix]

My doubt is if the there are more delays it is only additive in nature right? So, I can't understand this concept...

[shubhangisingh]

Why is setup not affecting during negative hold?

[rupamandal]

the explanation was awesome, good job :-))