How CPUs do Out Of Order Operations - Computerphile

How CPUs that are capable can manage to complete tasks simultaneously without the program knowing. Matt Godbolt continues his series on how processors work.

This video was filmed and edited by Sean Riley.

[momomi]

A better example than a sausage factory, is a film production, all the scenes are filmed out of order, based on locations, crew availabilty etc..
But as long as the editing is ordering the scenes in the script's order (program) the result for the viewer will be acceptable

[gojohnniegogo]

Bonus points for a Winamp reference. Topical too since the source code is being released in September!

[qfytidw]

It's crazy how Tomasulo's algorithm for out of order execution was was first used in the IBM System/360 Model 91 released in 1967, predating the integrated circuit.

[MattGodbolt]

I see folks are speculating on the topic already ;)

[jaffarbh]

Simply brilliant. I would highly suggest covering Intel's "Itanium" CPU, and why it went awfully wrong.

[RKelleyCook]

Love me the robots where W == waiting and W == working.

[frankbucciantini]

Years later someone finally explaining the Spectre / Meltdown bug properly. This is why software mitigations make the CPUs affected much slower: they limit if not disable entirely this kind of mechanism.

[unvergebeneid]

The times where a sqrt would take 100 cycles are long gone. These days it's more on the order of 16-20 cycles. Still slow compared to a multiply or add but in the ballpark of a division.

[DubioserKerl]

Hang on, I know that logo on the shirt.... is that...? Yes, it IS Godbolt!

[SimGunther]

Modern x86 CPUs will have a RISC kind of pipeline in the microcode level despite the base ISA not implying such pipelining.

So to answer the main question, technically the CPU is doing (N core * pipeline phases / average cycles per instruction) things all at once, but that's not a neat answer since hyperthreading is possible and not all instructions run equally as latency from prediction rollbacks, cache locality/coherency, and write interference need to be considered, among many other things.

[JobvanderZwan]

The timing of this video is interesting: Lynn Conway, the computer scientist who invented some of the fundamental techniques for out-of-order execution in the 1960s, passed away at the beginning of June.

[IceMetalPunk]

As a web dev, this reminds me a ton of database transactions. You can update many columns in many rows in a database table at once, but if one fails, the transaction fails as a whole; it's "undone" because the changes never get committed to the database in the first place.

[nicksamek]

This series has been fantastic so far!

[bloated_complacency]

I have taken uni courses here in the statesbthat are not as clear and concise as this video has been. Thank you so much for this breakdown, it has added some much needed perspective into my computer science endeavors; keep up the great work!

[marcwinner]

Thanks so much for these videos. Matt is truly a great teacher of these concepts!

[sussteve]

"Well I feel like this is a i don't know if you've ever watched Qi where the big bell goes-"

[gekko]

Thanks Computerphile, I've been loving these series on how CPUs work. Absolutely fascinating, even for a layperson like me

[chaoslab]

Coding assembly on the first few Archimedes machines was very interesting, multiple logical options with instructions (like conditional execution and barrel shifting).

[jeromethiel]

Winamp, it whips the llamas ass! ^-^ What a blast from the past.

[bemk]

This something you don't generally need, but when you do need it it's very useful to have. Had a bug the other day in an embedded system where the file system chip would put data on the bus despite its driver never asking for it, because an RSA calculation somehow triggered a speculative read in the chip's DMA region. Debugging was infuriating, 'cause every time you'd change some code to do an inspection, or would even interfere with a debugger, you'd interfere with the pipeline causing the bug to disappear. Only reason we ended up finding the solution was due to some very kind and skilled people in some forums all over the internet and an erratum for the chip