The Genius of RISC-V Microprocessors - Erik Engheim - ACCU 2022

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The Genius of RISC-V Microprocessors - Erik Engheim - ACCU 2022

RISC-V has been called the Linux of microprocessors, but RISC-V is a lot more than an open instruction-set architecture. It is also a radical departure from established industry conventions.

We will delve into what makes the RISC-V design profoundly different from other industry standards such as x86 and ARM and how that translates into significant advantages in the design of embedded systems as well as specialized hardware for tasks such as high-performance computing and machine learning.
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Erik Engheim

Erik is a principal consultant who got started with Amiga Basic and 68K Assembly back in the late 80s and early 90s. He has since been programming in every possible language from AVR Assembly to Go, Swift and Julia.

Erik is a book author, video course creator, and regular writer at Medium about almost anything from programming, rocket engines, space colonization, technology, UX, cryptocurrency, and history to calculating airship lifting capacity.
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#accuconf #programming #microprocessor

[robonator]

11:15 how the *_hell_* has no-one mentioned this before?! That single fact is insanely huge and yet I've *_never_* heard anyone mention it. The constant lingering issue I've always worried about regarding RISC was the risk that people wouldn't really standardize and everyone would just spin off their own little custom projects without the whole thing ever moving forward, but integrated intercompatibility features like that is insanely good. Making a desktop/laptop CPU for instance, you could make the chip, add an extension which you think makes things better, then write a micro-simulator for that instruction, upstream it to the linux kernel, and boom, everyone using your chip gets high-performance and everyone not using your chip doesn't get incompatibilities. (yeah MS/Apple are probably not going to have this apply to them, but they can be left in the dust trying to make everything themselves)

[sparshpriyadarshi]

this was such a good refresher on computer architecture.

[ClearerThanMud]

@4:38 "And that has a cost, not in dollars ..." YES in dollars. More instructions => more transistors => greater chip area => lower yields => higher cost. Lower yields both because the part is larger and because the chances of a defect in the part scale with the area.

[KennethScharf]

Actually there are (or were) operating system extensions for some X86 instructions (floating point), but now that ALL X86 processors include floating point this probably is no longer a thing.

[TymexComputing]

I like the idea of Fusion - and the idea of x0 (r0 ) - the DEV/NULL register is my favourite - it has never failed and is the fastest :) - even faster than XOR

[sejtano]

this is really great, especially considering that the x86 microprocessor has become a kind of emulator of an x86 at this point, they should go back a few generations, since, unlike the risc-v, they lost their way at some point

[dkutagulla]

Excellent talk!
This is what i bult in my senior year comp arch course

[disgruntledtoons]

If you look at it, the humble 6502 was the first RISC CPU. It had competition (6800, Z80, 6809, 8008/8080), but its minimized register count and minimized instruction set made it very simple to implement efficiently, and it could do everything that any other 8-bit CPU could do, and often just as quickly.

[TaweechaiMaklay]

Nice explaination for RISC-V and CISC,

[sgramstrup]

For me its enough that its supposed to be the 'Linux of processors', but the insights to how it works makes it better.

[isaacdorfman]

36:00
Micro operations as in micro-manage rather than micro-meter.
When you micro-manage you use more words than regular management.

[psikeyhackr]

I was a Customer Engineer for IBM and the term MICROCODE was used regularly regarding the System 32 and 34. I must have asked a couple of dozen people and noe one could explain it.

[Anders]

I didn't know that the RISC-V instruction set was so much smaller than for ARM. RISC-V being much leaner than ARM I guess could mean for example many more CPU cores on the same die.

[WildEngineering]

I built a RISCV32I core in a game called logic world. its my most recent upload to date.

[mytech]

Ha! He says don't think of it like Linux, because libre open-source is not the interesting part. Then imediately describes the same modular benefits that give Linux its advantages. Either looking at the kernel with loadable modules and customizable compile options, or looking at a full GNU OS with mix and match utilities. All only viable because they are built on libre IP.

[MoTheG]

I did not get the macro fusion part. Where does that happen?
If it happens inside the CPU then how does that help code density?

[MaxQ]

The analogy with two sports cars and many trucks would make so much more sense, and analogy, if it were two semi trucks vs many small trucks. The semi is optimal when it is fully loaded, going from A to B. But in real life computing they are rarely fully occuopied. The small trucks will have a much better utilization.

[kayakMike]

Nothing new or brilliant, but a solid design that allows scalability and customizations through modular extensions.

[tonysofla]

WCH has risc-v mcu's from 10cents up to $3 that has 480mbsp usb and 100Mb ethernet.

[blablamannetje]

At 05:30 ... isn't that comparing apples and oranges? The full 32bit of x86 (very usable, with all features, including floating point and SIMD) against the RV32I (which is Integer only, AFAIK)