PD Lec 40 - Well Tap Cell | VLSI | Physical Design

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This is a 40th video on VLSI Physical Design Series. In this video we have explained about well tap cell and CMOS latch up problem. This is a phenomenon which occurs inside of std cell and must be understood thoroughly.
Please ask your doubts in comments.

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Комментарии
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Hi Sir, appreciate the video..but the cursor is too small, maybe you can consider make it bigger.

Anyway thanks for the videos.

ahmadkhalid
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00:02 Understanding Well Tap Cell as a remedy for CMOS latch-up issue
00:35 CMOS latch-up can cause power to ground short.
01:10 Parasitic elements in PNP and NPN transistors
01:46 Substrate and well resistance in VLSI
02:22 Current flows through the emitter terminal when tapped, bypassing high-resistance
02:55 Importance of good tap in VLSI design
03:28 A Shorter standard cell with a separate capsule was introduced for tapping
04:04 Standard cells are designed with tapless nodes to avoid CMOS latch-up.

MedhanshMamidi
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How does the tap cell lower the resistance value of the substrate?

njason
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i think you have connected source of N channel FET with Vdd ?. or perhaps source and drain are changeable.

Shahidsoc
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Only one well tap cell in a row should be enough right ? , since all the std cells in a row are connected then, Why multiple well tap are required to be placed in a row?

ephznqy
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After tapping, Rsub comes in parallel with which resistance??

ephznqy