PD Lec 39 - CMOS Latch Up | VLSI | Physical Design

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This is a 39th video on VLSI Physical Design Series. In this video we have explained about CMOS latch up problem. This is a phenomenon which occurs inside of std cell and must be understood thoroughly.
Please ask your doubts in comments.

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Here's a link for Full STA series [till advanced level]:

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This is a very important topic and also a concern. Thanks for sharing 😀👍

Narennmallya

Finally i understood the concept of CMOS Lathup

shubhamsharma

for output of cmos inverter we take drain of both pmos and nmos right? but you considered output as source to drain

jammuashish

you have taken wrong connection in this video you have to take both Pmos and Nmos drains are connected that are out both nmos source is conncetd to vdd and pmos source is connected to vss gate is input

raghavendrakumar

For output of the CMOS inverter, Drain of PMOS and NMOS should be connected and output should be taken from that

piyushmohapatra

You have wrong connection in the nMOS device, the connected terminal should be the drain and not the source of the device.

Mhero

Shouldn't the shorted line of drain and drain be the output ?

sumaiaakterritu

nice explanation btw which background music you are using?, its so smoothing

jatingupta

Output connection is wrong sir . The Drain of both pmos and nmos are connected together to output . You shorted the Source of pmos with Drain of nmos !

vnnmichael

input isnt connected to parasitic transistors, so why input > Vdd will affect ?

prithvikrishna

This is a more complicated lecture compared to the previous set up til now

chahalpawanpreet

Please check pmos source terminal connected to vdd & Nmos source terminal connected to vss
We get output from connection of both pmos nmos drain terminal

agastinrajece

Hi sir,

Please cover indetailed information of SVT, HVT, LVT cells?

bhaskarpalagani

Sir can you please explain guard rings concept

mekalagowthami

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