Master AXI protocol: AXI READ 2 BYTE length (4KB crossing)

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This Video takes you through transaction analysis of 2 byte AXI read issued to first four and last four location of 4 KB slave address range.

You will also learn how the address crossing the data bus width and 4KB address boundary results in different from execution on the AXI bus. How the ordering rules are utilized.

Learn/Test your AXI understanding further:
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For 0x1ffc, shouldn't the transaction have a ARsize = 1? Same for 0x2000

etchbhatia