Working of JFET (Negative Voltage at the Gate)

Analog Electronics: Working of JFET (Negative Voltage at the Gate)
Topics Covered:
1. Working of junction field effect transistor.
2. Working of JFET when the voltage between gate and source is negative (or less than zero) and the voltage between drain and source is greater than zero.
3. Effect on depletion region.

[isakkazimi]

I just wanted to take a moment to thank you for the fantastic tutorial on JFET! Your educational videos have truly made it easier for me to grasp the concepts and applications. I really appreciate your clear and straightforward explanations.

Thank you for sharing your knowledge, and for everything you do to help others learn. Looking forward to more insights from you!

Best regards,
Isak

[glitchy_star_classes]

sir u a re my inspiration without you i would not be able to live my life i am your biggest fan sir i cant live without you

[sanatarlekar]

Thank you sir, this was so helpful
my exam starts at 9, your video might pass me in exam.
THANK YOU

[SandeepKumar-dgfx]

at 5:01
there will be - at G, and +at S.

[prashantmakhecha]

sir ur videos are really very helpful we love it so plz upload more videos on remaining topics quickly sir we have our exams coming soon we need ur help very much

[ShivamPandey-dukk]

Thank you For such detailed explainatin.

[shweta]

Sir...you are doing a great job...
will you please upload videos related to MOSFET as soon as possible...

[adarsh]

8:02 if we have applied negative voltage to gate here why is the G (+) then?

[AvinashSingh-bkkg]

I think when a positive gate source voltage is applied at gate terminal of the n channel JFET, It will lead to the breaking of the Depletion layer as a result of which large amount of current will flow through the channel and will destroy the transistor.

[rks]

Dear sir please upload all videos of power system as possible as possible because it is so important

[hemasundar]

sir, please upload next to these videos within 1 week. because i have exam on 11th dec. so that i can write the entrance exam well...your classes useful for me a lot.thank you for your classes. but please upload videos on FET and CMOS also within 1 week.thank you

[DataCascade]

please upload all videos of JFET as soon as possilble as my semester is near :(

[islamicbayan]

Thanks for nice explanation but I have got one question. What is the significance of achieving saturation current ID at lower VDS?

[vishalchavda]

Great Explanation bro... but one thing... Gate is shown with positive sign.. that is not appropriate..
Gate is less positive than Drain as u correctly said.. so for that only positive sign should not appropriate...

[bustanatweene]

Sir, It would be very helpful for me
if you upload lectures on

[hillarymapondera]

Thanks a lot, Sir. In case 2 will I(Dss) be the same magnitude as that of case I when V(GS) exceeds the relative Pinch voltage of case 2

[HypeR_UtkarsH]

Are 'Drain' and 'Source' terminals are interchangeable in JFET?
If yes! Then why 'Source' and 'Drain' terminals are fixed for the physical device?

[gyanadesh]

Sir, in case of -ve (V)gs why the two depletion region do not touch because when depletion regions touch (I)d=0 even then the junctons are in reverse biased

[drigpalsingh]

What are current source and voltage sources in MOSFET ad above

[sumathiuppari]

What will happens, if Vds in case 2 is equal to Vdd in case 1