Stitching Via Deep Dive | PCB Layout

Tech Consultant Zach Peterson jumps into a stitching vias exploration in this video. He focuses specifically on their uses, as well as how to both size and space them correctly.

0:00 Intro
0:36 When to Use Stitching Vias
2:32 Tying Together Copper Pour
4:59 Grid Size?
6:57 Layer Transitions
10:31 Shielding
14:49 Checking the Buses

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[ThePaulus]

When adding gng vias to connect all the planes, I usually set the opasity of the planes to 50 basically giving you a view through all the planes/layers, so you can easily see the areas where you can add gnd stitching vias without having to move a lot.

[jangrooten]

To place additional vias and connect them properly you need of course copper from one layer to the other layer. To check this Altium Designer has a nice Design Rule. It is called ReturnPath and can be found in High Speed Section of your Design Rules.

[leeslevin]

Thank you Zach and Altuim Academy for another brilliant deep dive topic. I use stitching via's in my design for ground returns and tying ground layers etc. I never took into consideration the spacing shielding properties and would play around with the spacing not understanding exactly how and why, apart from reducing impedance.
Until now that was the extent of my knowledge on how to use stitching via's. 🙌👍

[lavixl]

As someone who's layed out a few pretty nice EVBs for sub 6Ghz RF products my main goal was always best return loss for my traces. Proper via spacing is very important when thinking of cpwg. When meeting a trace and SMA it's a pretty big challenge (no sharp corners, tear dropping preferred). VIA spacing is critical and also artwork on transitions from a trace to any other shape is almost as critical. When in doubt always talk to your fabricator. Loving these vids.

[nasibfahim]

Great video! Thank you very much.. I always used the vías super close one to the next one.. being so conservative has any inconvenience? On the other hand, why you use 2 when the DK is 4? Thanks!

[icestormfr]

Btw, doing the routing of hi-speed-signals (including I/Os with considerable short rise/fall times) early and placing the return vias at the same time when they swith layers can reduce later problems/overhead-work to add the return vias.

[happyhippr]

I'd love some info on via fill % during enig/ hasl.

I'm using stitching vias for thermal conductivity, and not sure on optimal size / qty to get best bang for buck, from standard via plating processes without extra fill complexity.

[Spectr]

Thank you very much for this video, Zach! I get pleasure when watch such videos

[maxsintar]

Hi Zach, why do L2-L5 have a cut out below the antenna trace. Is it because the idea was to make the antenna trace thicker by distancing gnd further away in the stack and hence use L6 as a reference for the coplanar wave guide?

[francescobernardini]

Hi, thanks a lot for your video.

I have a question: let's assume I have all my ground planes connected by the stitching vias, and let's assume my top plane has all the RF signals and no ground plane, because the reference is the second layer.

When I connect the GND of an IC from the top layer, should I use a buried vias from top layer to layer 2, or another stitching vias that crosses the whole stackup, or it makes no difference?
I know electrically it's the same, but maybe one is preferable from a noise perspective

thanks!

[RyanCoffey-ipfy]

I have a question about placing vias near low speed digital traces. You mentioned its necessary to "maintain a return path when crossing multiple layers"

I don't fully understand. Wouldn't the return current flow from the GND connection on whatever SPI IC the connections lead to? Why do you need it near the physical transition? Could you explain the physics here a bit? Thank you so much!

Very grateful for your videos.

[Stephenkim-mnlb]

The via shielding(top to second layer) for micro strip line, when the via is connection on top layer it is not working. Why?

[jimjjewett]

Why *must* layers 4-6 be symmetrical with 1-3 in terms of copper fill? Is it just a convention? Does it stave off some manufacturing problems?

[flaviohpo]

Hello Zach, do you consider Dk for what frequency in the calculations?

[dimonasua]

Hello Zach, thanks for the nice video! It would also be great to make it possible to check for the presence of stitching vias by Altiums DRC. I think the idea pitch already exists in bugcrunch for a long time. Probably needs a little push by an expert like you. :)

[ananthadattadhruva]

Can we integrate the following into this? As we know the stack up and the material properties loaded into the designer

1. Trace width calculator along with the impedance calculator
2. Via shielding of a net. (spacing calculated based on the stackup input)

kindly let me know if it already exisits or if we need such a tool.

[WinChester_Ltd]

Hi, can you please explain to me one more time because I didn't get. Via shielding prevents frequencies which are lower or higher than a calculated frequency?

[jimjjewett]

If you're already using a fence at 20 mils, why stitch at only 250 mil or 80 mil? Is it to make the design intent of the antenna feed stand out? Do the stitches, even when separated from traces, cause too much disruption to the planes? Do fab houses still charge per drill hit, even though that doesn't seem to show up in their online quotes? (Or do they if you stitch over most of the board?) Do they start charging at high volumes, so you want to avoid getting into the habit with prototypes?

[ftmmrbs]

hello, the dk for fr4 is 4.. then why did you divide 3e8 by 2?

[creedo]

what if my PCB contains multiple substrates how do i calculate my constant ?