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How does Computer Memory Work? 💻🛠
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Have you ever wondered why it takes time for computers to load programs or video games? Also, ever wonder why your computer uses both DRAM as well as SSDs when they both are used to store data?
Well, most of that time is spent moving data from a hard drive or SSD into DRAM or Dynamic Random Access Memory, which is the working memory inside your computer. In this video, we're going to take a very deep dive into DRAM. We'll see how it connects to other parts of your computer, and then we'll explore how DRAM can store gigabytes of data in nanoscopic capacitors. After that, we'll cover the three main operations of DRAM: Reading, Writing, and Refreshing. And finally, we'll dive deep into some more complex aspects of DRAM that make it so amazingly fast such as folded DRAM architecture. We'll also learn what burst buffers are, and why there are so many banks of DRAM memory cells.
Do you want to support in-depth engineering and technology education?
Table of Contents:
00:00 - Intro to Computer Memory
00:47 - DRAM vs SSD
02:23 - Loading a Video Game
03:25 - Parts of this Video
04:07 - Notes
06:10 - Intro to DRAM, DIMMs & Memory Channels
10:43 - Crucial Sponsorship
12:09 - Inside a DRAM Memory Cell
15:28 - An Small Array of Memory Cells
17:41 - Reading from DRAM
19:38 - Writing to DRAM
21:55 - Refreshing DRAM
23:16 - Why DRAM Speed is Critical
25:06 - Complicated DRAM Topics: Row Hits
26:21 - DRAM Timing Parameters
27:51 - Why 32 DRAM Banks?
29:17 - DRAM Burst Buffers
30:58 - Subarrays
32:02 - Inside DRAM Sense Amplifiers
34:24 - Outro to DRAM
Key Branches from this video are: How do Solid State Drives Work?
Erratum:
At 10m 08s : Cicruit || Should be Circuit
At 21m 54s : 32 Bank Groups || Should be 32 Banks.
Script, Modeling, Animation: Teddy Tablante
Twitter: @teddytablante
Animation: Mike Radjabov
Modeling: Prakash Kakadiya
Voice Over: Phil Lee
Music Editing: Luis Zuleta
Sound Effects: Paulo de los Cobos
Supervising Sound Editor and Mixer: Luis Huesca
Post with Adobe Premiere Pro
References:
DDR5 SDRAM. JEDEC Standard. JESD79-5 July 2020
Dr. Cutress, Ian. "Insights into DDR5 Sub-Timings and Latencies". Oct 6th, 2020.
Dr. El-Maleh, Aiman. "Functions and Functional Blocks: Digital Logic Design" College of Computer Sciences and Engineering. King Fahd University of Petroleum and Minerals.
Hajimiri, Ali. Et al. "Design Issues in Cross-Coupled inverter Sense Amplifier". IEEE. Stanford University 1998
IBM. Understanding DRAM Operation. IBM 1996.
Jacob, Bruce. NG, Spencer W. Wang, David T. "Memory Systems: Cache, DRAM, Disk." Elsevier Inc. 2008
Keeth, Brent. Baker, R Jacob. Johnson, Brian. Lin, Feng. "DRAM Circuit Design: Fundamental and High-Speed Topics." IEE Press 2008.
Kim, Yoongu et. Al. "A Case for Exploiting Subarray-Level Parallelism in DRAM". Carnegie Mellon University
Micron. "DDR4 SDRAM. MT40A4G4. MT40A2G8. MT40A1G16. 16Gb: x4, x8, x16 DDR4 SDRAM Features" Micron Technologies 2018
Micron. "DDR5 SDRAM Product Core Data Sheet DDR5SDRAM Features." Micron Technologies 2020
Ryan, Kevin J. Morzano, Christopher K. Li, Wen. "Write Data Masking for Higher Speed DRAMS" US Patent 6532180 B2 Mar. 11 2003.
Shilov, Anton. "SK Hynix Details DDR5-6400". ANANDTECH. Feb 26th, 2019.
Wikipedia contributors. "CAS Latency". "DDR5 SDRAM". "Dynamics Random-Access Memory". "Memory Timing". "Synchronous Dynamic Random-Access Memory". Wikipedia, The Free Encyclopedia. Wikipedia, The Free Encyclopedia, Visited Nov 2022
#DRAM #CPU #Computer
Well, most of that time is spent moving data from a hard drive or SSD into DRAM or Dynamic Random Access Memory, which is the working memory inside your computer. In this video, we're going to take a very deep dive into DRAM. We'll see how it connects to other parts of your computer, and then we'll explore how DRAM can store gigabytes of data in nanoscopic capacitors. After that, we'll cover the three main operations of DRAM: Reading, Writing, and Refreshing. And finally, we'll dive deep into some more complex aspects of DRAM that make it so amazingly fast such as folded DRAM architecture. We'll also learn what burst buffers are, and why there are so many banks of DRAM memory cells.
Do you want to support in-depth engineering and technology education?
Table of Contents:
00:00 - Intro to Computer Memory
00:47 - DRAM vs SSD
02:23 - Loading a Video Game
03:25 - Parts of this Video
04:07 - Notes
06:10 - Intro to DRAM, DIMMs & Memory Channels
10:43 - Crucial Sponsorship
12:09 - Inside a DRAM Memory Cell
15:28 - An Small Array of Memory Cells
17:41 - Reading from DRAM
19:38 - Writing to DRAM
21:55 - Refreshing DRAM
23:16 - Why DRAM Speed is Critical
25:06 - Complicated DRAM Topics: Row Hits
26:21 - DRAM Timing Parameters
27:51 - Why 32 DRAM Banks?
29:17 - DRAM Burst Buffers
30:58 - Subarrays
32:02 - Inside DRAM Sense Amplifiers
34:24 - Outro to DRAM
Key Branches from this video are: How do Solid State Drives Work?
Erratum:
At 10m 08s : Cicruit || Should be Circuit
At 21m 54s : 32 Bank Groups || Should be 32 Banks.
Script, Modeling, Animation: Teddy Tablante
Twitter: @teddytablante
Animation: Mike Radjabov
Modeling: Prakash Kakadiya
Voice Over: Phil Lee
Music Editing: Luis Zuleta
Sound Effects: Paulo de los Cobos
Supervising Sound Editor and Mixer: Luis Huesca
Post with Adobe Premiere Pro
References:
DDR5 SDRAM. JEDEC Standard. JESD79-5 July 2020
Dr. Cutress, Ian. "Insights into DDR5 Sub-Timings and Latencies". Oct 6th, 2020.
Dr. El-Maleh, Aiman. "Functions and Functional Blocks: Digital Logic Design" College of Computer Sciences and Engineering. King Fahd University of Petroleum and Minerals.
Hajimiri, Ali. Et al. "Design Issues in Cross-Coupled inverter Sense Amplifier". IEEE. Stanford University 1998
IBM. Understanding DRAM Operation. IBM 1996.
Jacob, Bruce. NG, Spencer W. Wang, David T. "Memory Systems: Cache, DRAM, Disk." Elsevier Inc. 2008
Keeth, Brent. Baker, R Jacob. Johnson, Brian. Lin, Feng. "DRAM Circuit Design: Fundamental and High-Speed Topics." IEE Press 2008.
Kim, Yoongu et. Al. "A Case for Exploiting Subarray-Level Parallelism in DRAM". Carnegie Mellon University
Micron. "DDR4 SDRAM. MT40A4G4. MT40A2G8. MT40A1G16. 16Gb: x4, x8, x16 DDR4 SDRAM Features" Micron Technologies 2018
Micron. "DDR5 SDRAM Product Core Data Sheet DDR5SDRAM Features." Micron Technologies 2020
Ryan, Kevin J. Morzano, Christopher K. Li, Wen. "Write Data Masking for Higher Speed DRAMS" US Patent 6532180 B2 Mar. 11 2003.
Shilov, Anton. "SK Hynix Details DDR5-6400". ANANDTECH. Feb 26th, 2019.
Wikipedia contributors. "CAS Latency". "DDR5 SDRAM". "Dynamics Random-Access Memory". "Memory Timing". "Synchronous Dynamic Random-Access Memory". Wikipedia, The Free Encyclopedia. Wikipedia, The Free Encyclopedia, Visited Nov 2022
#DRAM #CPU #Computer
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