DVD - Lecture 3: Logic Synthesis - Part 1

Bar-Ilan University 83-612: Digital VLSI Design
This is Lecture 3 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).

Lecture 3 is the first of two part overview of logic synthesis. The first lecture focuses on Standard Cell Libraries, which are an integral part of the synthesis process.

Lecture slides can be found on the EnICS Labs web site at:

All rights reserved:
Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University

[andrewekladious]

You are an amazing teacher and a great asset to the world of semiconductors. Thank you for these very informative lectures!

[hassangillani]

I am totally new to vlsi field and this series enabled my basic understanding about how does synthesis is done. Thanks and apperciated your effort and waiting for more :)

[sagarpatel]

Very thorough and informative lecture, presented in very efficient manner. This is the 1st one I have seen, eager to see rest of them. Can't thank you enough, your students are blessed! Keep up the good work :)

[siddhantyadav]

I have been able to crack interviews of multiple MNC because of the superb lecture delivered by you. Thanks for the selfless effort

[kanchanchoubey]

Thank you so much Sir, I am trying to get job in industry after 10 years of long gap and your lectures are helping me a lot. Can't say enough Thanks.

[krishnapatel]

Thank you, Professor, for the very informative lectures. I am finding it very helpful.

[workthamngan]

Hi Prof, your sharing has made my source of learning to be here always without going anywhere else. Really thankful for that.

Here, I have a quick question on the multibit cell. From your experience, where would be the best way to optimize multibit or the implementation should be starting with?

Implementation
1. synthesis : if here, which stages ?
2. If it is pnr: which stages?

Post-Implementation
1. What would need to be done in the floorplan in order to ensure the placement of multibit done perfectly without any issue in the power railing, congestion, area and timing.

I totally appreciate your kind reply here. You are the best !

[kcpractronics]

Thankyou very much for your wonderful explanation.
No one is teaching this concepts for fre and you did it.
Thank you this helps a lot for Freshers 🙏

[gouravsaini]

amazing lecture .. really helps me to learn more in this quarantine period
Thanks for the valueble information sir ..

[Hugo_Musk]

I love you Professor! This lecture save my life!! Thanks!!

[BlueMirchi]

Thanks for the amazing lecture. Hope to see more. Thanks!!!

[rickzhi]

Thank you for your lecture. I have learned a lot. Your lecture explained many of my previous questions.

[AmbarishJayakumar]

Great lecture.
What is the difference between NLDM and ECSM in Liberty models?

[golu]

Very very brief deep knowledge ...great words

[oguzerdal]

Dear Mr. Teman,
Thank you very much for sharing these great lectures with us. You are a great teacher and the presentation of the slides is of top quality.
I would be glad if you could answer my following question: I have come across an SDF file type which is an output of the synthesis stage. Do you explain this format in any of the lectures, or if not could you briefly explain the purpose and content of this file type?

[amleshkumar]

Dear Sir,
Thank you for great explanation. I have only LEF/DEF file from OpenAccess. OpenAccess does not provide netlist file (.V file). May I know how can I use it in Innovus for IR drop Simulation?
Thank you
Amlesh Kumar

[friendhueihuei]

Do you have lecture about how to manipulate the software tools in this lecture series? Thank you.

[sktiwari]

What's the reason for different results for the same design in two different synthesis execution?

[Amplify]

Very nice lecture! If only all profs would have your teaching style..

One question: You said that CCS means "Concurrent Current Source", but I heard it stands for "Composite Current Source". Do you know what's the correct term here?

[anuragec]

Hi ...Why uniquification is important in Synthesis?
Why we are doing uniquification in backend, when while writing Rtl, the instantiations will have different names anyhow .