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DVD - Lecture 3b: HDL Compilation
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Bar-Ilan University 83-612: Digital VLSI Design
This is Lecture 3 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).
Lecture 3 is the first of two part overview of logic synthesis. The first lecture focuses on Standard Cell Libraries, which are an integral part of the synthesis process.
Lecture 3b briefly touches on the place of compilation within the synthesis flow.
Lecture slides can be found on the EnICS Labs web site at:
All rights reserved:
Dr. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University
This is Lecture 3 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).
Lecture 3 is the first of two part overview of logic synthesis. The first lecture focuses on Standard Cell Libraries, which are an integral part of the synthesis process.
Lecture 3b briefly touches on the place of compilation within the synthesis flow.
Lecture slides can be found on the EnICS Labs web site at:
All rights reserved:
Dr. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University
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