RISC-V ISA: Understanding Limitations and Methods to Improve Code Density & Performance

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The whole "dereference lots of constant pointers" thing is something lots of compilers/ISAs handle badly. E.g. on ARMv6M, if you are accessing 0x40..0, 0x40...4 and so on, GCC will stick a constant under your function for each of these pointers, and then pull them in with PC-relative loads. If you put your registers in a struct, you instead get a single base pointee generation, and small offsets encoded in the loads and stores. Interesting to see the parallels :)

Wasting bit 5 of the c.addi immediate on a sign bit was an interesting choice from the RISC V designers. I guess it is related to the bodies of code AW analysed; I would have guessed a 6 bit unsigned would be more useful than 6 bit signed, even though you lose your 16-bit decrement instruction.

Wren

RISC-V ISA: Understanding Limitations and Methods to Improve Code Density & Performance

RISC-V ISA: Understanding Limitations and Methods to Improve Code Density & Performance

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