The RISC-V News We've Been Waiting For: RVA23

One of the major limitations to RISC-V adoption is the fragmented ecosystem. An open source ISA is just that - open source and anyone can do what they want with it. There's no standard base for software developers to target, like they have with Arm and x86. However, as of October 2024, RISC-V International has ratified the RVA23 Profile Standard to enable that baseline support. It's going to be the first of many, but here's the information.

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Welcome to the TechTechPotato (c) Dr. Ian Cutress
Ramblings about things related to Technology from an analyst for More Than Moore

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[jaras]

Am I crazy or is the audio not synced properly?

I got similar impression when I watched AMD-Intel collaboration video.
Checked it on both TV and phone - same effect, it is very small but I'm pretty sure something is off...

[FinaISpartan]

I can't imagine a world without fused-multiply-add vector operator. Alot of software depends on it so I'm glad they added it into the new standard

[Elegant-Capybara]

This is exciting, can't wait to have a decently performant Risc-V SBC or Dev Kit

[MrAlanCristhian]

Always remember: standardization is better than perfection.

[jdp_man]

This is indeed incredibly important, looking at the spec. I've been wanting someone to implement RV64GCBVH and beyond for a couple years, to consider it a real desktop core. Also UEFI. This goes above that. It's gonna take Atleast a couple years to come out on shelves though!

[esra_erimez]

I'm such a nerd geeking out on a CPU ISA but there is something exciting about RISC-V to me

[Wild_Cat]

Pleaes do an interview with the Intel graphics driver team

[tonyolmstead]

What an incredible coincidence- I was JUST looking into the riscv spec literally hours before the press release.

Very excited to see this

[CyReVolt]

Note that the profiles do not define the platform for a general purpose OS.
The platform is implicitly defined via the SBI spec, which is driven by the BRS and PRS task groups (Boot/Platform Runtime Services), and by the actual implementation thereof, for which the spec still leaves some decisions open, e.g. which traps to delegate to S-mode and how to treat them otherwise.

[TechAmbr]

Fantastic news! Here's to an open computing future!

[pedrophmg]

SpacemiT K1 does support RVA22 in the most higher level, this does includes some hypervisor instructions as optional, hope its implemented there, this core can be found on Banana Pi BPI-F3, so its easy to access

[D.u.d.e.r]

Very cool, thx for the update! RISC-V is clearly growing on all fields👍

[davidjohnston]

I took a look at the RNG instructions (since I may have something to do with the RNG instructions in X86). I see they fall into the trap NIST laid by ratifying SP800-90A and SP800-90B but leaving SP800-90C unfinished. So they've defined an SP800-90B like thing when really you want an SP800-90C like thing. So for a certifiable RNG you are left with software post processing to finish the job, while being at risk of 90C changing to make your post processing non compliant in the future. This is a problem if you need to publish a spec now. It's worth identifying the subset of BSI that is also RBG2 and RBG3 compliant against the most recent draft 90C and going for that (that is what RdRand and RdSeed in X86 does) and specifying that for RISC-V. Then you are pretty safe since I got verbal assurances from NIST that the xor and RS RBG3 constructions in 90C will remain in the finalized 90C spec.

[KomradeMikhail]

Why is the official Standards document PDF hosted on a google drive link ?

Not quite as shady as making Presidential Executive Orders over twitter, but...

[udirt]

Hey there, would love if you could make an explanation how it could impact things like tenstorrents 5 minion cores. Just it would be good if i could understand it without a cs/math education.

Like, i know there will be extensions for advanced math stuff. And it was the breakthrough for most architectures (ppc altivec, x86 - mmx/sse)!

do people like tenstorrent somehow do the vector stuff at a higher level and don't need it? Or is it gonna give them a jump?

[mba]

I'm on phone, android with revanced, and there is an audio sync issue.

[MrHaggyy]

With AI/ML you are not getting around vector instructions or other forms of executing math in parallel. However even in regular compute they are useful. Cryptography, de/en coding audio/video or calculating a reasonable large sum. This is also huge for the embedded market, as it makes more projects feasible.

[ThorDyrden]

Is RVA23 supposed to be read "R Ve A" - or "R 5 A" - guess it stands for Risk Five Architecture 2023?

[TheLegitAlpha]

I think the other thing that needs to be done is translation of different instruction sets, especially since X86 and ARM are pretty big, and compatibility would be an issue.

[Bravo_Ventures_LLC]

0:42 not really. you can basically do that already with android and your pc. But is everybody doing it. Out of 100 people that I know, I'm the only one that does what I do, basically everything. For starters 28k views on a video with such topic is a very small fraction of even the 7 million people in my metropolitan area. But im from the silicon valley so plenty devs and the such out here. RISC V is an opportunity for "non groupie sell out" entrepreneurs to develop and gain a foothold in the market. That's where the open source supporters need to be united. Helping develop this technology further. You are right about one thing though: Doing what we want with it. I for sure plan to empower my people with the Development of LATINux™ and LATINos™.