Dynamic Random Access Memory (DRAM). Part 7: Memory Address Mapping

This is the seventh in a series of videos is about the fundamental principles of Dynamic Random Access Memory, DRAM, and the essential concepts of DRAM operation. This video illustrates how the individual bits of a memory address can be allocated among rows, columns and banks in order to control the interleaving of data bursts across multiple banks inside a single chip.

[wheatstone]

Thank you so much for this extremely clear, extremely helpful video series. I've recently started working in the DRAM industry as a designer and this video series is better than any internal training materials that we have. I will be forwarding this video series to all fellow new hires from now on. Thank you so much again, everything makes so much more sense now!!!

[princedavid]

Great Video Series.... Never seen such Graphical Representations which explain to minute details with Crystal Clear Clarity.

[이재연-iu]

The perfect videos for understanding DRAM. Thank you so much providing this high quality videos!!!

[aycho]

I'm a minute late to the party, but THANK YOU for the series! Was trying to 'refresh my memory' on DRAM. had trouble finding content not too basic or complex, until I ran into this. So packed in value, especially for the time it takes to go through the series

[hugoneto]

Great DRAM Video Series. It's quite clear and very helpful to understand the main DRAM fundamentals.

[edwin]

Brilliant introduction to the inner mechanism of DRAM! Thank you!

[anuupadhyaya]

This was very much insighful, I'm thankful that it exists.

[johnwhittaker]

I design high speed boards for orbital spacecraft and aircraft, many DDR4 designs. This is an excellent series.

[jsyoon]

All loud and clear, the essence all learning materials shall have but don't. Thank you so much

[LRV-TECH]

This is the best explanation of DRAM Memory work on YouTube. Is this LAST video for DRAM memory? Will there be something similar in the future for 3D NAND memory?

[selvalooks]

Great series !! best in youtube for DRAM !!!

[badejavuade]

Thanks... very structured and detailed. It would be nice to follow up with an example DDR IC and Controller interface(72bit ECC) pointing out the connection alternatives for multiple rank configuration.

[gauravjain]

Amazing video with clear explanation on DRAM...Please post more on DRAM series

[animatrix]

There is some confusion I think, once you've activated a row, you can issue any amount of read bursts (n*bl8) to it since the row is still registered in the sense amps. Since there are quite a few columns you can do this quite a few times. Ofcourse you eventually will have to precharge/close the row due to refresh requirements and so forth.

This way of doing things is sometimes referred to as open page policy.

[oopss]

one more video about "dram memory controller" and this series will be perfect .

[abhishekravoor]

Thanks for this beautiful series on DRAM's😍😍

[iammituraj]

Super cool animations and explanation.

[Sythemn]

That's one elegant solution there.

[ryangao]

thanks for this lecture, so clear and easy to understand

[marcusthegamer]

Great video! May I ask how is having 9 bits possible? Aren't systems usually 4, 8, 16, 32 or 64 bit architecture?