Computer Architecture - Lecture 8: Data Retention, Memory Refresh and Memory Latency (Fall 2022)

Lecture 8a: Data Retention and Memory Refresh
Lecture 8b: Memory Latency
Date: October 21, 2022

Recommended Reading:
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Intelligent Architectures for Intelligent Computing Systems

A Modern Primer on Processing in Memory

RowHammer: A Retrospective

RECOMMENDED LECTURE VIDEOS & PLAYLISTS:
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Computer Architecture Fall 2021 Lectures Playlist:

Digital Design and Computer Architecture Spring 2022 Livestream Lectures Playlist:

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Interview with Professor Onur Mutlu:

The Story of RowHammer Lecture:

Accelerating Genome Analysis Lecture:

Memory-Centric Computing Systems Tutorial at IEDM 2021:

Intelligent Architectures for Intelligent Machines Lecture:

Computer Architecture Fall 2020 Lectures Playlist:

Digital Design and Computer Architecture Spring 2020 Lectures Playlist:

Public Lectures by Onur Mutlu, Playlist:

Computer Architecture at Carnegie Mellon Spring 2015 Lectures Playlist:

Rethinking Memory System Design Lecture @stanfordonline :

[joechang]

in the siloed IT industry, too many people cannot let go of the 1980's (up to late 90s) concept that more memory at lower cost was absolutely priority 1. During Intel Merced development, the 460GX chipset was going to support up to 64GB memory (depending). At the time, the top Merced was projected at $4.5K (Intel) so 18K for 4 processors, while the memory was looking at around $80K. Today, we are looking a top 64-core processor around $6K, while memory, assume $800 per 128GB DIMM, 16 DIMMs per socket, is $13K. Basically, memory cost is now small.
Now factor in that software is licensed per core and is much larger than hardware cost. The value of improved performance is huge. Yet we cannot let go of old memory concepts.
Getting a DRAM vendor to make a low latency DRAM chip is problematic with no forecastable demand.
Take a standard ECC DIMM. ex. the SPD knows the actual DRAM chips have 4 groups, 4 banks, 18 row address bits, and 10 columns address bits.
Can we write to the SPD to use only 17 row address bits? presumably this is low half of the bank? then determine an appropriate set of latencies?

[ABSplastic]

Oh, people online can't hear the questions.