Digital Design & Computer Architecture - Lecture 8: Timing and Verification (Spring 2022)

Lecture 8: Timing and Verification
Date: March 18, 2022
1 hour 52 minutes

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Rethinking Memory System Design Lecture @stanfordonline :

[DongWanYoon]

Thank you for the lecture. it's so helpful.

[YA_LUNNAYA_PONI]

28:10 I'm not exactly clear on why the second implementation omitted the 4-input OR gate. Like if you also omit that OR gate in first design the control signal propagation will be faster (and it's not like two AND gates can be enabled at the same time can they?)

[YA_LUNNAYA_PONI]

29:15 but the data propagation time here is worse than in the second design. So it's not like, unequivocally better.