Reusable SystemVerilog Testbench

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This video explains the need and concept of a configurable testbench. Also it explains how we implement the reusable testbench and testcases in SystemVerilog language. More importantly, how we generate different scenarios during simulation by running the testcases on same testbench.

VLSI Verification Course is a front end VLSI Course, with a good overview of functional verification methodologies and SystemVerilog language. It explains the details of building a class-based verification environment using SystemVerilog HDVL.

This course is unique and is completely based on a standard testbench architecture that can be used for creating SystemVerilog testbenches. And they can be easily migrated to the UVM framework. Also, we use two main examples throughout the course to explain all the methodology and language concepts. One is a small dual-port RAM RTL design which is used for explaining all the language concepts in detail, especially for the testbench implementation. The other one is a complex SOC design which is used for explaining the use-cases of certain SystemVerilog language features and challenges of migrating IP level testbenches to SOC level testbenches.

Modules:
* Verification Methodology Overview
* SystemVerilog for Verification
* Universal Verification Methodology Overview

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