Systemverilog generate : Where to use generate statement in Verilog & Systemverilog

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Very simple explanation, Thank you so much for your hard work, keep posting more such videos. Thanks alot

ravisoni

sir, Does modules in generate block will execute concurrently or sequentially? if concurrently how to use generate for interdependent modules.

harsha

can there be nested generate statements? if yes then what will be the name for the instantiated module

tanujsharma

Can we use generate block inside the functions, like if we have recursive call?

lakshmikanthk

hi,
i have tried the same scenario without providing generate block.but still getting output without any error.could please explain me why?

noufalnishath

Systemverilog generate : Where to use generate statement in Verilog & Systemverilog

Systemverilog generate : Where to use generate statement in Verilog & Systemverilog

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