Timing Constraints in Sequential Synchronous Circuits

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This is a tutorial on timing in sequential synchronous circuits composed of edge-triggered flip flops and combinational logic. In this video, I present some timing constraints and show how to ensure that they are satisfied.

Table of contents:
00:00 - Introduction
00:34 - Timing diagrams
03:11 - Flip flop timing
08:35 - Flip flop with feedback
15:48 - Linearization of flip flop paths
17:23 - Flip flop with more complicated feedback
18:52 - More complicated example
24:21 - Conclusion

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Next level explaintion after searching entire youtube final I got the video Tnx alot

rohankademani

Wow! Absolutely phenomenal, this was an amazing lecture. Thanks so much. Things are now much clearer

alexmathai

Thanks for this tutorial, long time puzzle solved!

taoxia

Best video on the topic... All the other videos wasn't as comprehensive as this.

nadarasarbahavan

Wow!thanks, this has never been so easier

ilgapr

Thank you so much! Now I understand my homework.

mariancrofts

Thank you so much, excellent explanation!

TheDoubin

Thank you, It really helped me a lot.

aishwaryanair

This was a great tutorial! Very helpful and very well done. I love the tip at the very end as well. Thank you.

I have one question though, how come you didn't say contamination delay (tcd) instead of minimum propagation delay (tpd min)?

WonderCloudHD

Very nicely explained. Could you also do a video on clock domain crossing and metastability?

anamaykane

Must watch before starting sequential....

PawanBhakuni

At 23:54 shouldn't it be t-ccq for the hold-time constraint?

db

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