SystemVerilog Tutorial in 5 Minutes - 03 Numerical Variables

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00:00 Intro
00:09 reg, wire, logic, bit, byte, shortint, int, longint, integer
01:22 Example - 2 states variable vs 4-states variable
02:30 Example - Signed number vs unsigned number
02:56 Example - Counter with signed number
03:46 typedef
  1. Open Logic
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After trying with different numbers, I went back to the original and it gave me the correct result!

[2025-01-03 21:11:04 UTC] iverilog '-Wall' '-g2012' design.sv testbench.sv && unbuffer vvp a.out
The two are equal
Done

I don't actually know what went wrong.
Thank you.




Edited:
Just realized that I used 225 instead of 255. That's my problem.

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