SystemVerilog Tutorial in 5 Minutes - 09a Function / Task Argument

00:00 Intro
00:12 Argument direction
00:50 Input argument
01:55 Output argument
02:35 Inout argument
03:17 Ref argument
03:57 Return value vs output argument
04:19 Return value with function name

[harry]

Thank you so much for all the SV tutorial! Is the slide open to the public by any chance?

[SKins]

Thanks alot for the video, though i have a question, i tried coding this to display the a and b values, but the printed values in the eda simulator happens to be as below. which doesn't match with the video above. is the default value of a = 0 or is it x since its an output int?thanks in advance.
a=x
a=0
a=1
b=1

module automatic test();

task mytask(output int a);
$display("a=%0d", a);

#1;
a++;
$display("a=%0d", a);

#1;
a++;
$display("a=%0d", a);

endtask

int b;

initial begin
b=1;
mytask(b);
$display("b=%0d", b);
end
endmodule