Floorplanning in VLSI Physical Design

In this video, we provide an in-depth overview of key concepts related to Floorplanning in VLSI Physical Design. We begin by outlining the design flow and its connection to floorplanning, focusing on the goals and objectives that guide an effective floorplan. The discussion then moves into the various techniques and optimizations involved in floorplanning, including the use of a floorplan tree and constraint graph pair to improve layout efficiency. Additionally, we cover topics such as floorplan sizing, presented in two stages, and the importance of linear ordering, explored through distinct steps. Finally, advanced methods like cluster growth and simulated annealing are introduced, highlighting their roles in achieving optimal floorplan results.

Chapters for easy navigation:
00:00 Beginning & Intro
00:41 Chapter Index
04:48 Design Flow & Floorplanning
07:09 Goals for Floorplan
09:00 Optimization in Floorplanning
11:57 Floorplan Tree
15:24 Constraint Graph Pair
19:35 Floorplan Sizing – I
22:36 Floorplan Sizing – II
23:57 Linear Ordering – I
26:19 Linear Ordering – II
28:29 Linear Ordering – III
29:12 Cluster Growth
30:00 Simulated Annealing


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This video suggests:
"Overview of floorplanning in VLSI Physical Design"
"Key goals and objectives of effective floorplanning"
"How floorplanning fits into the VLSI design flow"
"Techniques and optimizations for efficient floorplanning"
"Using floorplan trees and constraint graphs in layout design"
"Importance of linear ordering in floorplanning"
"Step-by-step guide to floorplan sizing in VLSI design"
"Stages of floorplan sizing explained"
"Advanced floorplanning methods for VLSI"
"Cluster growth technique in floorplanning optimization"
"Simulated annealing for optimal floorplanning results"
"How to achieve layout efficiency in VLSI floorplanning"
"Floorplan tree and constraint graph pair: A detailed guide"
"Best practices for floorplanning in physical design"
"Linear ordering steps in VLSI floorplanning"
"Exploring the cluster growth method in chip design"
"Introduction to simulated annealing for floorplanning"
"Video tutorial on floorplanning techniques and tools"
"Connection between design flow and floorplanning objectives"
"Strategies for optimizing floorplans in VLSI Physical Design"

[Dragon_Company]

Hello my friends. I have encountered the following problem:
There is a way to fix a Setup Violation called Register Duplication - by duplicating registers, the timing paths can be shortened, reducing the wire and cell propagation delays.

This can be done in the following ways - Duplication can be done manually in the RTL or automatically by the synthesis and PnR tools.

I have not found a way to do this in PnR tools (Innovus). Maybe you can tell me?