Advanced Process Technologies - Part 2: Fabricating a FinFET

This is part 2 of my lecture on Advanced Process Technologies.

In this lecture, I introduce advanced process technologies based on FinFET (Tri-gate) structures. In the lecture, I start with the motivation for the move to the "third-dimension" and then overview the primary mechanisms for fabricating a deeply scaled (22nm and below) FinFET device in comparison with traditional planar device fabrication. This leads to the perspective of FinFETs from a designers point of view, taking a look at the features of these new devices and process nodes and focusing on transistor layout, layout-dependent effects (LDEs) and device parasitics. I wrap up my talk with a look to the near-future with the current trends of gate-all-around (GAA) nano-sheet (nano-ribbon) devices and buried power rails.

Many thanks to Alvin Loke for his great tutorials on these subjects in recent years and Or Nahum, who taught me a lot about the process aspects of deep nanoscale fabrication.

All rights reserved:
Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University

[SandyMMMM]

I am a layout engineer. Your videos are the best. I want to watch them 10 times. Thank you so much!

[ahmedabdelhakeem]

Thank you so much for such informative content ❤️

[rabhiselma]

Thank you so much really your courses helped me a lot

[felipemagalhaes]

Incredibly informative! Thank you! You helped me a lot to understand it :)

[JoeLion]

As mentioned at 12:20, why do multi-patterned layers have to be unidirectional? Is it because the mask geometry doesn't work, in that you can't really "shift" the pattern in 2 directions? Or, something about how you grow the spacers that only works in one direction at a time?

[sagarkore]

Its really helpful thank you so much for such quality content

[yushanyeh]

Thank you much!! It really helps a lot !

[UmairuddinAshraf]

1:54 pattern our gates or pattern our fins???

Since we are not viewing the finfet substrate from the same angle shown for planer substrate (left figure)

[DM]

31:55 why couldn't via sizes just match the metal dimensions so that the connection from one metal to a higher/lower metal doesn't have a bottleneck due to via size?

[TheKkreddy]

Thank you very much !!!much appreciated ...

[fromto]

Could tell me why we put HfO2 above the source and drain? How that makes current flow?

[Akshay-xoiy]

Hello! Please help me understand how a cell height in a standard cell is defined. What is a metal 2 and what are the tracks?

[saipranavg]

Hi Adi,
When we say 7nm device of FinFET type,
does it mean the channel length in 7nm ??

[vikassh]

Can you please make a playlist for these lectures thankyou

[yingtang]

Hi Adam, I have a question on the doping step in finFET, I dont see it in your animation. isn't it needed?

[qiyu]

Professor, is there any link to download your videos? It's very useful for our work